module clk_gen(
			input		rstn,
			input           clk,
			output		clk_div16_0,
			output		clk_div16_1,
			output		clk_div16_2,
			output		clk_div16_3,
			output		clk_div16_4,
			output		clk_div16_5,
			output		clk_div16_6,
			output		clk_div16_7,
			output		clk_div16_8,
			output		clk_div16_9,
			output		clk_div16_a,
			output		clk_div16_b,
			output		clk_div16_c,
			output		clk_div16_d,
			output		clk_div16_e,
			output		clk_div16_f,

                        output          clk_h,
                        output          clk_l
		);

reg  [3:0]      cnt_ini;
always@(posedge clk or negedge rstn)
        if(!rstn)
                cnt_ini <=      4'd0;
        else if(cnt_ini <=   4'd7)
                cnt_ini <=      cnt_ini + 4'd1;
        else
                cnt_ini <=      cnt_ini;
wire    div_en;
assign  div_en  =       (cnt_ini ==4'd8)? 1'b1:1'b0;

reg  [3:0]      cnt_0;
reg  [3:0]      cnt_1;
reg  [3:0]      cnt_2;
reg  [3:0]      cnt_3;
reg  [3:0]      cnt_4;
reg  [3:0]      cnt_5;
reg  [3:0]      cnt_6;
reg  [3:0]      cnt_7;
reg  [3:0]      cnt_8;
reg  [3:0]      cnt_9;
reg  [3:0]      cnt_a;
reg  [3:0]      cnt_b;
reg  [3:0]      cnt_c;
reg  [3:0]      cnt_d;
reg  [3:0]      cnt_e;
reg  [3:0]      cnt_f;

always@(posedge clk or negedge rstn)
        if(!rstn) begin
                cnt_0    <=       4'h0;
                cnt_1    <=       4'h1;
                cnt_2    <=       4'h2;
                cnt_3    <=       4'h3;
                cnt_4    <=       4'h4;
                cnt_5    <=       4'h5;
                cnt_6    <=       4'h6;
                cnt_7    <=       4'h7;
                cnt_8    <=       4'h8;
                cnt_9    <=       4'h9;
                cnt_a    <=       4'ha;
                cnt_b    <=       4'hb;
                cnt_c    <=       4'hc;
                cnt_d    <=       4'hd;
                cnt_e    <=       4'he;
                cnt_f    <=       4'hf;
         end
         else if(div_en) begin
        	cnt_0	<=	cnt_0     +       4'd1;
        	cnt_1	<=	cnt_1     +       4'd1;
        	cnt_2	<=	cnt_2     +       4'd1;
        	cnt_3	<=	cnt_3     +       4'd1;
        	cnt_4	<=	cnt_4     +       4'd1;
        	cnt_5	<=	cnt_5     +       4'd1;
        	cnt_6	<=	cnt_6     +       4'd1;
        	cnt_7	<=	cnt_7     +       4'd1;
        	cnt_8	<=	cnt_8     +       4'd1;
        	cnt_9	<=	cnt_9     +       4'd1;
        	cnt_a	<=	cnt_a     +       4'd1;
        	cnt_b	<=	cnt_b     +       4'd1;
        	cnt_c	<=	cnt_c     +       4'd1;
        	cnt_d	<=	cnt_d     +       4'd1;
        	cnt_e	<=	cnt_e     +       4'd1;
        	cnt_f	<=	cnt_f     +       4'd1;
         end       
         else begin
        	cnt_0	<=	cnt_0;
        	cnt_1	<=	cnt_1;
        	cnt_2	<=	cnt_2;
        	cnt_3	<=	cnt_3;
        	cnt_4	<=	cnt_4;
        	cnt_5	<=	cnt_5;
        	cnt_6	<=	cnt_6;
        	cnt_7	<=	cnt_7;
        	cnt_8	<=	cnt_8;
        	cnt_9	<=	cnt_9;
        	cnt_a	<=	cnt_a;
        	cnt_b	<=	cnt_b;
        	cnt_c	<=	cnt_c;
        	cnt_d	<=	cnt_d;
        	cnt_e	<=	cnt_e;
        	cnt_f	<=	cnt_f;

        end

assign  clk_div16_0     =       cnt_0[3];
assign  clk_div16_1     =       cnt_1[3];
assign  clk_div16_2     =       cnt_2[3];
assign  clk_div16_3     =       cnt_3[3];
assign  clk_div16_4     =       cnt_4[3];
assign  clk_div16_5     =       cnt_5[3];
assign  clk_div16_6     =       cnt_6[3];
assign  clk_div16_7     =       cnt_7[3];
assign  clk_div16_8     =       cnt_8[3];
assign  clk_div16_9     =       cnt_9[3];
assign  clk_div16_a     =       cnt_a[3];
assign  clk_div16_b     =       cnt_b[3];
assign  clk_div16_c     =       cnt_c[3];
assign  clk_div16_d     =       cnt_d[3];
assign  clk_div16_e     =       cnt_e[3];
assign  clk_div16_f     =       cnt_f[3];


reg   [3:0]  cnt_div16;
always@(posedge clk_div16_0 or negedge rstn)
           if(!rstn)
                   cnt_div16    <=      4'd0;
           else if(div_en)
                   cnt_div16    <=      cnt_div16       +       4'd1;
           else
                   cnt_div16    <=      cnt_div16;


assign  clk_h   =       clk_div16_0;
assign  clk_l   =       cnt_div16[0];

endmodule
