module TB();

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end

reg		clk;
reg		rstn;
reg		en;
reg	[15:0]	din_in;	
reg	[21:0]	cnt;


initial	begin

		#0;
		rstn	= 1'b0;
		clk =  1'b0;
		din_in  =	1'b0; 
		en  =	1'b0; 
		#300;
		rstn	=	 1'b1;

end

always #200 clk = ~clk;


always@(posedge clk or negedge rstn)
		if(!rstn)
			cnt	<=	22'd0;
		else
			cnt	<=	cnt + 22'd1;


initial	begin
	wait(cnt[17]==1'b1)
			$finish(0);
end
always@(posedge clk or negedge rstn) 
begin
		if(cnt >= 2047 ) 
			   begin
				en    <= 	1'b1;
			    end
		else
			    begin
				en    <= 	1'b0;
			     end
end


reg	[47:0]		fcw;

initial	begin
		fcw	=	48'h0840_0000_0000;
end

wire   [15:0]     cos;
wire   [15:0]     sin;


NCO	inst_nco_0(
                 		.clk				(clk  		),
                 		.rstn				(rstn		),
                 		.phase_manual_clr		(1'b0		),
                 		.phase_auto_clr			(1'b0		),
                 		.fcw				(fcw		),
                 		.pha				(16'd0		),
                 		.cos	                        (cos            ),
                 		.sin	                        (sin            )
                	);


wire	[15:0]	dout_p0;
wire	[15:0]	dout_p1;

MeanIntp2		inst_MeanIntp2
		       (
				.clk			(clk	                ),
				.rstn			(rstn			),
				.en			(en			),
                                .din	                (cos & {16{en}}     ),           
				.dout_m			(dout_p0                ),
				.dout_o			(dout_p1                )
		        );

reg	[15:0]	cs_wave;

always@(posedge clk)	cs_wave	 	= dout_p1;
always@(negedge clk)	cs_wave	 	= dout_p0;

endmodule                                                                        	
                                                                                 	
                                                                                 	

