
`timescale 1ns/1ps

module TB();

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, TB);
end

    
    reg         clk;
    reg         rst_n;
    reg  [15:0] din;
    reg         enable;
    reg  [21:0] cnt;
    wire [15:0] dout0;
    wire [15:0] dout1;

    
    s2p_2 uut (
        .clk    (clk),
        .rst_n  (rst_n),
        .din    (din),
        .en (enable),
        .dout0 (dout0),
        .dout1 (dout1)
    );

reg[15:0]  din_r1;
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        din_r1 <= 0;
    end
    else begin
        din_r1 <= din;
    end
end

wire signed [15:0] diff;
assign diff = din - din_r1;

reg[15:0]  dout1_r1;
reg[15:0]  dout1_r2;
always  @(posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        dout1_r1 <= 0;
        dout1_r2 <= 0;
    end
    else begin
        dout1_r1 <= dout1;
        dout1_r2 <= dout1_r1;

    end
end

wire  signed [15:0] diff12;
wire  signed [15:0] diff23;
assign  diff12 = dout0 - dout1_r2;
assign  diff23 = dout1 - dout0;
    
    initial begin
        rst_n = 0;
        enable = 0;
        clk = 1'b0;
        din = 16'h0000;

        
        #20;
        rst_n = 1;

        
        #10;

    end

    
    always #5 clk = ~clk; 

    
    always @(posedge clk or negedge rst_n) begin
        if (rst_n == 1'b0) begin
            cnt <= 22'd0;
        end else begin
            cnt <= cnt + 22'd1;
        end
    end

    
reg [15:0] enable_cnt;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        enable <= 0;
        din <= 16'd0;
        enable_cnt <= 0;  
    end else begin
        
        if (cnt < 1000) begin  
            if (enable_cnt == 0) begin
                if ($urandom % 2 == 0) begin 
                    enable <= 1;
                    enable_cnt <= $urandom % 10 + 5;  
                    din <= $urandom; 
                end else begin
                    enable <= 0;
                    din <= 16'd0;  
                end
            end else begin
                
                enable <= 1;
                enable_cnt <= enable_cnt - 1; 
                din <= $urandom; 
            end
        end else begin
            enable <= 0;  
            din <= 16'd0;  
        end
    end
end

    
    initial begin
        wait(cnt[11] == 1); 
        $finish;
    end


endmodule
