184 lines
7.3 KiB
Python
184 lines
7.3 KiB
Python
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import numpy as np
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import os
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import copy
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from FourChZreg_define import *
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class FourChZChipConfig(object):
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CHANNEL_OFFSET = 0x00600000
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SCALE_FACTOR = 2 ** 31
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def __init__(self, mk_instance, **kwargs):
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self.mk = mk_instance
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self.FolderName = kwargs.get('FolderName')
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self.config_file = kwargs.get('config_file')
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def write_registers_batch(self, register_values):
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"""批量写入寄存器"""
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if isinstance(register_values, dict):
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register_values = register_values.items()
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for address, value in register_values:
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self.mk.rw_once('w', address, value, self.config_file)
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def write_register(self, address, value):
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self.mk.rw_once('w', address, value, self.config_file)
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def _calculate_tc_coefficients(self, **kwargs):
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tc_coef_set = kwargs.get('tc_coef_set')
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coef_set = TC_COEFFICIENT_SETS[tc_coef_set]
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amp_real = coef_set['amp_real']
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amp_imag = coef_set['amp_imag']
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time_real = coef_set['time_real']
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time_imag = coef_set['time_imag']
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sampling_rate = 3e9
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coef1, coef2 = [], []
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for ar, ai, tr, ti in zip(amp_real, amp_imag, time_real, time_imag):
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amp_coef = ar + 1j * ai
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time_coef = tr + 1j * ti
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coef1.append(amp_coef * np.exp(1e9 / sampling_rate / 2 / (1 - amp_coef) * time_coef) / (1 - amp_coef))
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coef2.append(np.exp(1e9 / sampling_rate / (1 - amp_coef) * time_coef))
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return {
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'alpha_re': [int(c.real * self.SCALE_FACTOR) for c in coef1],
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'alpha_im': [int(c.imag * self.SCALE_FACTOR) for c in coef1],
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'beta_re': [int(c.real * self.SCALE_FACTOR) for c in coef2],
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'beta_im': [int(c.imag * self.SCALE_FACTOR) for c in coef2]
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}
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def _general_reg_config(self, **kwargs):
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# 深拷贝 kwargs 保护原始字典
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kwargs = copy.deepcopy(kwargs)
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# 自定义寄存器配置支持
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if 'custom_registers' in kwargs:
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custom_registers = kwargs.pop('custom_registers')
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first_item = custom_registers[0]
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if isinstance(first_item, tuple):
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self.write_registers_batch(custom_registers)
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elif isinstance(first_item, dict):
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for item in custom_registers:
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self.write_register(item['addr'], item['values'])
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elif isinstance(first_item, list):
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for item in custom_registers:
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self.write_register(item[0], item[1])
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# 芯片工作模式配置
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if 'chip_mode' in kwargs:
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chip_mode = kwargs.pop('chip_mode')
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if chip_mode == 'RAMP':
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self._ramp_config(**kwargs)
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elif chip_mode == 'AWG':
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self._awg_config(**kwargs)
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def _ramp_config(self, **kwargs):
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# 统一使用相对基地址（动态适配当前 Channel）
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channel = kwargs.get('channel')
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ctrl_base = addr_base['CTRL0_BASE'] + channel * 0x600000
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['MODDOTR'], 8) # 切换到RAMP输出
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ramp_ctrl = kwargs.get('ramp_ctrl')
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if ramp_ctrl == 'MCU': # RAMP连到 mcu_regfile
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['SPI_RAMPENR'], 1 << 30)
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elif ramp_ctrl == 'SPI': # RAMP连到 ctrl_regfile
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ramp_spi_registers = []
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fixed_enable = kwargs.get('fixed_enable', False)
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if fixed_enable: # 固定值模式
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fixed_value = kwargs.get('fixed_value', 0)
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ramp_spi_registers += [1 << 15 | fixed_value << 16]
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# 写寄存器函数自带了通道偏移
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['SPI_RAMPFIXR'], ramp_spi_registers)
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else: # 斜坡模式
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height = kwargs.get('height', 0)
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length = kwargs.get('step_time', 0)
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ramp_spi_registers += [0 << 15]
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ramp_spi_registers += [height << 16]
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ramp_spi_registers += [length]
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['SPI_RAMPFIXR'], ramp_spi_registers)
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# 配置使能
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['SPI_RAMPENR'], 1 << 31 | 0 << 30)
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def _awg_config(self, **kwargs):
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channel = kwargs.get('channel', 0)
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ctrl_base = addr_base['CTRL0_BASE'] + channel*0x600000
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tcco_base = addr_base['TCCO0_BASE'] + channel*0x600000
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dtcm_base = addr_base['DTCM0_BASE'] + channel*0x600000
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mode_map = {'nco': 6, 'nco_fm': 7, 'env': 4, 'mod': 5}
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mode = kwargs.get('mode', None)
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moddotr_val = mode_map.get(mode, 0)
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# 1. DSP (拖尾矫正) 配置
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tail_en = kwargs.get('tail_en', False)
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if tail_en:
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coefficients = self._calculate_tc_coefficients(**kwargs)
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tc_coef_registers = (
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coefficients['alpha_re'] +
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coefficients['alpha_im'] +
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coefficients['beta_re'] +
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coefficients['beta_im']
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)
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self.write_register(tcco_base + FourChZreg_define['tc_reg']['TCPARR0'], tc_coef_registers)
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tccdr_addr = tcco_base + FourChZreg_define['tc_reg']['TCCDR']
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for i in range(8):
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self.write_register(tccdr_addr, 1 << i)
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moddotr_val &= ~4 # 把[2]清零
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# 2. 数据选择寄存器 MODDOTR 配置
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['MODDOTR'], moddotr_val)
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# 3. 调制使能寄存器 MODENR 配置
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amp_mod_enable = kwargs.get('amp_mod_enable', False)
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freq_mod_enable = kwargs.get('freq_mod_enable', False)
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bias_enable = kwargs.get('bias_enable', False)
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mod_enable = (
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(int(not bias_enable) << 0)
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| (int(not freq_mod_enable) << 1)
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| (int(not amp_mod_enable) << 2)
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)
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self.write_register(ctrl_base + FourChZreg_define['ctrl_reg']['MODENR'], mod_enable)
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# 4. mcu_regfile 配置
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mcu_registers = []
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fcw_list = kwargs.get('fcw', [0])
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mcu_reg_clr = kwargs.get('mcu_reg_clr', False)
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pcw_list = kwargs.get('pcw', [0])
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for fcw in fcw_list:
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mcu_registers.append(int(fcw / fs / 4 * 2 ** 32))
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mcu_registers.append(1 << 31 if mcu_reg_clr else 0 << 31)
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for pcw in pcw_list:
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mcu_registers.append(int(pcw / 360 * (2 ** 16 - 1)) << 16)
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rz_pha = kwargs.get('rz_pha', 0)
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mcu_registers.append(int(rz_pha / 360 * (2 ** 16 - 1)))
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ff_amp_list = kwargs.get('ff_amp', [0])
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fm_amp_list = kwargs.get('fm_amp', [0])
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for ff, fm in zip(ff_amp_list, fm_amp_list):
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mcu_registers.append(((ff & 0xFFFF) << 16) | (fm & 0xFFFF))
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bias_list = kwargs.get('bias', [0])
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for bias in bias_list:
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mcu_registers.append(bias << 16)
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self.write_register(dtcm_base + FourChZreg_define['mcu_reg']['CWFR0'], mcu_registers)
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# 5. FMER 配置
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fm_en = kwargs.get('fm_en', False)
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self.write_register(dtcm_base + FourChZreg_define['mcu_reg']['FMER'], 1 << 31 if fm_en else 0)
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return None
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def config_chip_reg(mk_instance, **kwargs):
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config = FourChZChipConfig(mk_instance, **kwargs)
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config._general_reg_config(**kwargs)
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