Chip_Case_Generator/4ch-Z_Generator/FourChZreg_define.py

# TODO: 寄存器统一由excel表格维护
# TODO: 寄存由excel表格生成
FourChZreg_define = {
    'sys_reg': {
        'IDR': 0x00,
        'VIDR': 0x04,
        'DATER': 0x08,
        'VERR': 0x0C,
        'TESTR': 0x10,
        'IMR': 0x14,
        'ISR': 0x18,
        'SFRTR': 0x1C,
        'SFRR': 0x20,
        'CH0RSTR': 0x24,
        'CH1RSTR': 0x28,
        'CH2RSTR': 0x2C,
        'CH3RSTR': 0x30,
        'DBGCFGR': 0x34,
        'MISR': 0x40,
        'SYNCR': 0x44,
        'MSDENR': 0x48,
        'MSDPCNTR': 0x4C,
    },
    'ctrl_reg': {
        'MCUPARAR0': 0x00,
        'MCUPARAR1': 0x04,
        'MCUPARAR2': 0x08,
        'MCUPARAR3': 0x0C,
        'MCURESR0': 0x10,
        'MCURESR1': 0x14,
        'MCURESR2': 0x18,
        'MCURESR3': 0x1C,
        'RTIMR': 0x98,
        'ICNTR': 0x9C,
        'FSIR': 0xA0,
        'MODMR': 0x100,
        'MODENR': 0x104,
        'MODDOTR': 0x108,
        'MIXODFR': 0x10C,
        'STR': 0x110,
        'NCOAOR': 0x114,
        'SPI_RAMPFIXR': 0x118,
        'SPI_RAMPSR': 0x11C,
        'SPI_RAMPIFSR': 0x120,
        'SPI_RAMPENR': 0x124,
        'TSTIMER': 0x130,
        'TSITVLR': 0x134,
        'TSENR': 0x138,
        'TSVALR': 0x13C,
    },
    'mcu_reg': {
        'CWFR0': 0x40,
        'CWFR1': 0x44,
        'CWFR2': 0x48,
        'CWFR3': 0x4C,
        'CWPRR': 0x50,
        'GAPR0': 0x54,
        'GAPR1': 0x58,
        'GAPR2': 0x5C,
        'GAPR3': 0x60,
        'GAPR4': 0x64,
        'GAPR5': 0x68,
        'GAPR6': 0x6C,
        'GAPR7': 0x70,
        'LCPR': 0x74,
        'AMPR0': 0x78,
        'AMPR1': 0x7C,
        'AMPR2': 0x80,
        'AMPR3': 0x84,
        'BIASR0': 0x88,
        'BIASR1': 0x8C,
        'BIASR2': 0x90,
        'BIASR3': 0x94,
        'RTIMR': 0x98,  # Note: Same as in ctrl_reg
        'ICNTR': 0x9C,  # Note: Same as in ctrl_reg
        'FSIR': 0xA0,   # Note: Same as in ctrl_reg
        'DCBVR': 0xA4,
        'FMER': 0xB4,
        'MCU_RAMPFIXR': 0xB8,
        'MCU_RAMPSR': 0xBC,
        'MCU_RAMPIFSR': 0xC0,
        'MCU_RAMPENR': 0xC4,
        'PRNGSDR': 0xC8,
        'PRNGRESR': 0xCC,
        'MULTR0': 0xD0,
        'MULTR1': 0xD4,
        'DTFR': 0xD8,
    },
    'tc_reg': {
        'TCPARR0': 0x000,
        'TCPARR1': 0x004,
        'TCPARR2': 0x008,
        'TCPARR3': 0x00C,
        'TCPARR4': 0x010,
        'TCPARR5': 0x014,
        'TCPARR6': 0x018,
        'TCPARR7': 0x01C,
        'TCPAIR0': 0x020,
        'TCPAIR1': 0x024,
        'TCPAIR2': 0x028,
        'TCPAIR3': 0x02C,
        'TCPAIR4': 0x030,
        'TCPAIR5': 0x034,
        'TCPAIR6': 0x038,
        'TCPAIR7': 0x03C,
        'TCPBRR0': 0x040,
        'TCPBRR1': 0x044,
        'TCPBRR2': 0x048,
        'TCPBRR3': 0x04C,
        'TCPBRR4': 0x050,
        'TCPBRR5': 0x054,
        'TCPBRR6': 0x058,
        'TCPBRR7': 0x05C,
        'TCPBIR0': 0x060,
        'TCPBIR1': 0x064,
        'TCPBIR2': 0x068,
        'TCPBIR3': 0x06C,
        'TCPBIR4': 0x070,
        'TCPBIR5': 0x074,
        'TCPBIR6': 0x078,
        'TCPBIR7': 0x07C,
        'TCBPR': 0x080,
        'TCCER': 0x084,
        'TCOVR': 0x088,
        'TCCDR': 0x08C,
    },
    'pll_reg': {
        'INTPLL_REFCTRL'  : 0x00,
        'INTPLL_PCNT'     : 0x04,
        'INTPLL_PFDCTRL'  : 0x08,
        'INTPLL_SPDCTRL'  : 0x0C,
        'INTPLL_PTATCTRL' : 0x10,
        'INTPLL_SELCTRL'  : 0x14,
        'INTPLL_VCOCTRL'  : 0x18,
        'INTPLL_TCCTRL'   : 0x1C,
        'INTPLL_AFCCTRL'  : 0x20,
        'INTPLL_AFCFBCTRL': 0x24,
        'INTPLL_AFCLDCNT' : 0x28,
        'INTPLL_DIVRSTSEL': 0x2C,
        'INTPLL_TESTCLK'  : 0x30,
        'INTPLL_DIGCLKSEL': 0x34,
        'INTPLL_STATUS'   : 0x38,
        'INTPLL_SYNC'     : 0x3C,
        'INTPLL_UPDATE'   : 0x40,
        'INTPLL_CLKRXPD'  : 0x44,
        'INTPLL_RESV'     : 0x48,
        'CCALRSTR'        : 0x4C,
        'CCALATENR'       : 0x50,
        'CCALSELALNR'     : 0x54,
        'CCALDCCQECR'     : 0x58,
        'CCALQECCT0R'     : 0x5C,
        'CCALQECCT1R'     : 0x60,
        'CCALDCCCT0R'     : 0x64,
        'CCALDCCCT1R'     : 0x68,
        'DIVSYNCDCR'      : 0x6C,
        'SYNCCLRENR'      : 0x70,
        'CCALDCCCT2R'     : 0x74,
        'CCALSTR'         : 0x78,
    }
}

# Usage example:
# value = reg_define['sys_reg']['DATER']  # Gets 0x00
# print(f"IDR value: {value}")
# import reg_define

# 预定义的TC系数组
TC_COEFFICIENT_SETS = {
    'default': {
        'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': '默认TC系数组'
    },
    'coef1': {
        'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': 'lsw - coef1'
    },
    'coef2': {
        'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
        'time_imag': [0, -1/300, -1/500, 0, 0, 0, 0, 0],
        'description': 'lsw - coef2'
    },
    'coef3': {
        'amp_real': [0.025, 0.009, 0.0002, 0.2, 0, 0, 0, 0],
        'amp_imag': [0, 0.012, 0, 0, 0, 0, 0, 0],
        'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
        'time_imag': [0, -1/300, -1/500, 0, 0, 0, 0, 0],

        'description': 'lsw - coef3'
    },
    'coef4': {
        'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-1/250, -1/2000, -1/1600, -1/20, 0, 0, 0, 0],
        'time_imag': [0, -1/15, -1/50, 0, 0, 0, 0, 0],
        'description': 'lsw - coef4'
    },
    'coef5': {
        'amp_real': [0.0281, 0.0024, 0.0021, 0.0011, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-0.0033, -0.0027, -0.0027, -0.0002, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': 'czy - coef5'
    },
    'coef6': {
        'amp_real': [0.0314, 0.0132, 0.0055, 0.0017, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-0.0096, -0.0021, -0.0009, -0.0002, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': 'czy - coef6'
    },
    'coef7': {
        'amp_real': [0, 0.0282, 0, 0.0130, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-0.0193, -0.0051, -0.0012, -0.0020, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': 'czy - coef7'
    },
    'coef8': {
        'amp_real': [0.0314*1, 0.0132*1, 0.0055*1, 0.0017*1, 0.0282*1, 0.0130*1, 0.0024*1, 0.0021*1],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [-0.0096, -0.0021, -0.0009, -0.0002, -0.0051, -0.0020, -0.0027, -0.0027],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': 'thfu - coef8'
    },
    'coef9': {
        'amp_real': [0.0314*1, 0.0132*1, 0.0055*1, 0.0017*1, 0.0282*1, 0.0130*1, 0.0024*1, 0.0021*1],
        'amp_imag': [0.012, 0.012, 0.012, 0.012, 0.012, 0.012, 0.012, 0.012],
        'time_real': [-0.0096, -0.0021, -0.0009, -0.0011, -0.0051, -0.0020, -0.0027, -0.0027],
        'time_imag': [-1/300, -1/500, -1/15, -1/20, -1/100, -1/200, -1/400, -1/800],
        'description': 'thfu - coef9'
    },
    'custom': {
        'amp_real': [0, 0, 0, 0, 0, 0, 0, 0],
        'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_real': [0, 0, 0, 0, 0, 0, 0, 0],
        'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
        'description': '自定义系数组 - 需要手动设置'
    }
}


#### regfile base address ####
addr_base = {
    'SYST_BASE':   0x00000000,
    'DBGM_BASE':   0x01900000,

    'ITCM0_BASE':  0x00100000,
    'DTCM0_BASE':  0x00200000,
    'CTRL0_BASE':  0x00300000,
    'TCCO0_BASE':  0x00301000,
    'ENVI0_BASE':  0x00400000,
    'ENVM0_BASE':  0x00500000,
    'CLK0_BASE':   0x01F00000,
    'DAC0_BASE':   0x01F01000,

    'ITCM1_BASE':  0x00700000,
    'DTCM1_BASE':  0x00800000,
    'CTRL1_BASE':  0x00900000,
    'TCCO1_BASE':  0x00901000,
    'ENVI1_BASE':  0x00A00000,
    'ENVM1_BASE':  0x00B00000,
    'CLK1_BASE':  0x01F02000,
    'DAC1_BASE':  0x01F03000,


}

# 共用是SYST_BASE 基地址，前5个地址其实就是偏移地址夹600000，后面两个其实是加1000


fs = 750 #MHz