279 lines
8.3 KiB
Python
279 lines
8.3 KiB
Python
# TODO: 寄存器统一由excel表格维护
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# TODO: 寄存由excel表格生成
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FourChZreg_define = {
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'sys_reg': {
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'IDR': 0x00,
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'VIDR': 0x04,
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'DATER': 0x08,
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'VERR': 0x0C,
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'TESTR': 0x10,
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'IMR': 0x14,
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'ISR': 0x18,
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'SFRTR': 0x1C,
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'SFRR': 0x20,
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'CH0RSTR': 0x24,
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'CH1RSTR': 0x28,
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'CH2RSTR': 0x2C,
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'CH3RSTR': 0x30,
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'DBGCFGR': 0x34,
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'MISR': 0x40,
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'SYNCR': 0x44,
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'MSDENR': 0x48,
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'MSDPCNTR': 0x4C,
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},
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'ctrl_reg': {
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'MCUPARAR0': 0x00,
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'MCUPARAR1': 0x04,
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'MCUPARAR2': 0x08,
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'MCUPARAR3': 0x0C,
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'MCURESR0': 0x10,
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'MCURESR1': 0x14,
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'MCURESR2': 0x18,
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'MCURESR3': 0x1C,
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'RTIMR': 0x98,
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'ICNTR': 0x9C,
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'FSIR': 0xA0,
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'MODMR': 0x100,
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'MODENR': 0x104,
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'MODDOTR': 0x108,
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'MIXODFR': 0x10C,
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'STR': 0x110,
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'NCOAOR': 0x114,
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'SPI_RAMPFIXR': 0x118,
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'SPI_RAMPSR': 0x11C,
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'SPI_RAMPIFSR': 0x120,
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'SPI_RAMPENR': 0x124,
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'TSTIMER': 0x130,
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'TSITVLR': 0x134,
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'TSENR': 0x138,
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'TSVALR': 0x13C,
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},
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'mcu_reg': {
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'CWFR0': 0x40,
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'CWFR1': 0x44,
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'CWFR2': 0x48,
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'CWFR3': 0x4C,
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'CWPRR': 0x50,
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'GAPR0': 0x54,
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'GAPR1': 0x58,
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'GAPR2': 0x5C,
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'GAPR3': 0x60,
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'GAPR4': 0x64,
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'GAPR5': 0x68,
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'GAPR6': 0x6C,
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'GAPR7': 0x70,
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'LCPR': 0x74,
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'AMPR0': 0x78,
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'AMPR1': 0x7C,
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'AMPR2': 0x80,
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'AMPR3': 0x84,
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'BIASR0': 0x88,
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'BIASR1': 0x8C,
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'BIASR2': 0x90,
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'BIASR3': 0x94,
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'RTIMR': 0x98, # Note: Same as in ctrl_reg
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'ICNTR': 0x9C, # Note: Same as in ctrl_reg
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'FSIR': 0xA0, # Note: Same as in ctrl_reg
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'DCBVR': 0xA4,
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'FMER': 0xB4,
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'MCU_RAMPFIXR': 0xB8,
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'MCU_RAMPSR': 0xBC,
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'MCU_RAMPIFSR': 0xC0,
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'MCU_RAMPENR': 0xC4,
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'PRNGSDR': 0xC8,
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'PRNGRESR': 0xCC,
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'MULTR0': 0xD0,
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'MULTR1': 0xD4,
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'DTFR': 0xD8,
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},
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'tc_reg': {
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'TCPARR0': 0x000,
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'TCPARR1': 0x004,
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'TCPARR2': 0x008,
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'TCPARR3': 0x00C,
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'TCPARR4': 0x010,
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'TCPARR5': 0x014,
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'TCPARR6': 0x018,
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'TCPARR7': 0x01C,
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'TCPAIR0': 0x020,
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'TCPAIR1': 0x024,
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'TCPAIR2': 0x028,
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'TCPAIR3': 0x02C,
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'TCPAIR4': 0x030,
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'TCPAIR5': 0x034,
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'TCPAIR6': 0x038,
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'TCPAIR7': 0x03C,
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'TCPBRR0': 0x040,
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'TCPBRR1': 0x044,
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'TCPBRR2': 0x048,
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'TCPBRR3': 0x04C,
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'TCPBRR4': 0x050,
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'TCPBRR5': 0x054,
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'TCPBRR6': 0x058,
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'TCPBRR7': 0x05C,
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'TCPBIR0': 0x060,
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'TCPBIR1': 0x064,
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'TCPBIR2': 0x068,
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'TCPBIR3': 0x06C,
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'TCPBIR4': 0x070,
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'TCPBIR5': 0x074,
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'TCPBIR6': 0x078,
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'TCPBIR7': 0x07C,
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'TCBPR': 0x080,
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'TCCER': 0x084,
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'TCOVR': 0x088,
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'TCCDR': 0x08C,
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},
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'pll_reg': {
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'INTPLL_REFCTRL' : 0x00,
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'INTPLL_PCNT' : 0x04,
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'INTPLL_PFDCTRL' : 0x08,
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'INTPLL_SPDCTRL' : 0x0C,
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'INTPLL_PTATCTRL' : 0x10,
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'INTPLL_SELCTRL' : 0x14,
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'INTPLL_VCOCTRL' : 0x18,
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'INTPLL_TCCTRL' : 0x1C,
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'INTPLL_AFCCTRL' : 0x20,
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'INTPLL_AFCFBCTRL': 0x24,
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'INTPLL_AFCLDCNT' : 0x28,
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'INTPLL_DIVRSTSEL': 0x2C,
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'INTPLL_TESTCLK' : 0x30,
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'INTPLL_DIGCLKSEL': 0x34,
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'INTPLL_STATUS' : 0x38,
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'INTPLL_SYNC' : 0x3C,
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'INTPLL_UPDATE' : 0x40,
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'INTPLL_CLKRXPD' : 0x44,
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'INTPLL_RESV' : 0x48,
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'CCALRSTR' : 0x4C,
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'CCALATENR' : 0x50,
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'CCALSELALNR' : 0x54,
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'CCALDCCQECR' : 0x58,
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'CCALQECCT0R' : 0x5C,
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'CCALQECCT1R' : 0x60,
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'CCALDCCCT0R' : 0x64,
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'CCALDCCCT1R' : 0x68,
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'DIVSYNCDCR' : 0x6C,
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'SYNCCLRENR' : 0x70,
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'CCALDCCCT2R' : 0x74,
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'CCALSTR' : 0x78,
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}
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}
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# Usage example:
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# value = reg_define['sys_reg']['DATER'] # Gets 0x00
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# print(f"IDR value: {value}")
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# import reg_define
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# 预定义的TC系数组
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TC_COEFFICIENT_SETS = {
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'default': {
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'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': '默认TC系数组'
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},
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'coef1': {
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'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': 'lsw - coef1'
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},
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'coef2': {
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'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
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'time_imag': [0, -1/300, -1/500, 0, 0, 0, 0, 0],
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'description': 'lsw - coef2'
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},
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'coef3': {
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'amp_real': [0.025, 0.009, 0.0002, 0.2, 0, 0, 0, 0],
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'amp_imag': [0, 0.012, 0, 0, 0, 0, 0, 0],
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'time_real': [-1/250, -1/650, -1/1600, -1/20, 0, 0, 0, 0],
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'time_imag': [0, -1/300, -1/500, 0, 0, 0, 0, 0],
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'description': 'lsw - coef3'
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},
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'coef4': {
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'amp_real': [0.025, 0.015, 0.0002, 0.2, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-1/250, -1/2000, -1/1600, -1/20, 0, 0, 0, 0],
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'time_imag': [0, -1/15, -1/50, 0, 0, 0, 0, 0],
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'description': 'lsw - coef4'
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},
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'coef5': {
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'amp_real': [0.0281, 0.0024, 0.0021, 0.0011, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-0.0033, -0.0027, -0.0027, -0.0002, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': 'czy - coef5'
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},
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'coef6': {
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'amp_real': [0.0314, 0.0132, 0.0055, 0.0017, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-0.0096, -0.0021, -0.0009, -0.0002, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': 'czy - coef6'
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},
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'coef7': {
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'amp_real': [0, 0.0282, 0, 0.0130, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-0.0193, -0.0051, -0.0012, -0.0020, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': 'czy - coef7'
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},
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'coef8': {
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'amp_real': [0.0314*1, 0.0132*1, 0.0055*1, 0.0017*1, 0.0282*1, 0.0130*1, 0.0024*1, 0.0021*1],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [-0.0096, -0.0021, -0.0009, -0.0002, -0.0051, -0.0020, -0.0027, -0.0027],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': 'thfu - coef8'
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},
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'coef9': {
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'amp_real': [0.0314*1, 0.0132*1, 0.0055*1, 0.0017*1, 0.0282*1, 0.0130*1, 0.0024*1, 0.0021*1],
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'amp_imag': [0.012, 0.012, 0.012, 0.012, 0.012, 0.012, 0.012, 0.012],
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'time_real': [-0.0096, -0.0021, -0.0009, -0.0011, -0.0051, -0.0020, -0.0027, -0.0027],
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'time_imag': [-1/300, -1/500, -1/15, -1/20, -1/100, -1/200, -1/400, -1/800],
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'description': 'thfu - coef9'
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},
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'custom': {
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'amp_real': [0, 0, 0, 0, 0, 0, 0, 0],
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'amp_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_real': [0, 0, 0, 0, 0, 0, 0, 0],
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'time_imag': [0, 0, 0, 0, 0, 0, 0, 0],
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'description': '自定义系数组 - 需要手动设置'
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}
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}
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#### regfile base address ####
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addr_base = {
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'SYST_BASE': 0x00000000,
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'DBGM_BASE': 0x01900000,
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'ITCM0_BASE': 0x00100000,
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'DTCM0_BASE': 0x00200000,
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'CTRL0_BASE': 0x00300000,
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'TCCO0_BASE': 0x00301000,
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'ENVI0_BASE': 0x00400000,
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'ENVM0_BASE': 0x00500000,
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'CLK0_BASE': 0x01F00000,
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'DAC0_BASE': 0x01F01000,
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'ITCM1_BASE': 0x00700000,
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'DTCM1_BASE': 0x00800000,
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'CTRL1_BASE': 0x00900000,
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'TCCO1_BASE': 0x00901000,
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'ENVI1_BASE': 0x00A00000,
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'ENVM1_BASE': 0x00B00000,
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'CLK1_BASE': 0x01F02000,
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'DAC1_BASE': 0x01F03000,
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}
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# 共用是SYST_BASE 基地址，前5个地址其实就是偏移地址夹600000，后面两个其实是加1000
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fs = 750 #MHz |