[dprof-info] generating timeline profile dprof.dir/timeline.txt
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Mar 13 18:07 2026
*Verdi* Loading libsscore_vcs201809.so
FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019
(C) 1996 - 2019 by Synopsys, Inc.
*Verdi* FSDB: The switch FSDB file size might not match the input size (500MB) because of performance concerns.
*Verdi* FSDB: To have the FSDB file size match the input size (500MB), set the FSDB_ENV_PRECISE_AUTOSWITCH environment, though the dumping performance might decrease.
*Verdi* : Enable automatic switching of the FSDB file.
*Verdi* : (Filename='./verdplus', Limit Size=500MB, File Amount=1000000).
*Verdi* : Create FSDB file './verdplus_000.fsdb'
*Verdi* : Create the file './verdplus.log' to log the time range of each FSDB file.
*Verdi* : Create virtual FSDB file './verdplus.vf' to log each FSDB file.
*Verdi* : Begin traversing the scopes, layer (0).
*Verdi* : End of traversing.
*Verdi* : Begin traversing the MDAs, layer (0).
*Verdi* : Enable +mda and +packedmda dumping.
*Verdi* : End of traversing the MDAs.
========================================
Testbench started at 0
========================================
Phase 1: Training with correct patterns...
Link ready at 104675000
Phase 2: Sending a correct frame...
WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a00000000000000000000000000000000000000000000000 mask=fffffffffff00000
Write detected: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
Error: "../../sim/lvds/TB.sv", 311: TB: at time 106695200 ps
Unexpected write address: 292
Error: "../../sim/lvds/TB.sv", 312: TB: at time 106695200 ps
Byte mask mismatch: 0000000fffffffff
Error: "../../sim/lvds/TB.sv", 313: TB: at time 106695200 ps
Byte mask high part not zero: 0000000f
Correct frame write verified.
WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
Phase 3: Sending a frame with bad CRC...
WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a0000000a000000fa000000ea000000da000000ca000000b mask=fffffffffff00000
CRC error detected at 109615000
WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
CRC_ERROR pulse at 109625000
Link down as expected.
Phase 4: Re-training...
Link ready again.
WRITE: addr=291 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000003a0000002a0000001a0000000a000000fa000000ea000000da000000ca000000b mask=fffffffffff00000
WRITE: addr=292 data=a000000aa0000009a0000008a0000007a0000006a0000005a0000004a0000013a0000012a0000011a0000010a000000fa000000ea000000da000000ca000000b mask=0000000fffffffff
Phase 5: Testing delay_tap adjustment...
Final delay_tap = 3
Phase 6: Testing with descrambler enabled (header not scrambled)...
Link ready for scrambled data.
WRITE: addr=291 data=a000000aa0000009b0000009b0000008b0000007b0000006b0000005b0000004b0000003b0000002b0000001b0000000a000000ea000000da000000ca000000b mask=00ffffffffff0000
Scrambled test passed (no CRC error).
========================================
Testbench finished at 127115000
========================================
$finish called from file "../../sim/lvds/TB.sv", line 463.
$finish at simulation time            127115000
[dprof-info] generating dprof summary report in dprof.txt
           V C S   S i m u l a t i o n   R e p o r t 
Time: 127115000 ps
CPU Time:      0.340 seconds;       Data structure size:   0.1Mb
Fri Mar 13 18:07:28 2026
