*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
Command arguments:
    +define+verilog
    -sverilog
    -f filelist_vlg.f
        ../../rtl/comm/sirv_gnrl_xchecker.v
        ../../rtl/comm/sirv_gnrl_dffs.v
        ../../rtl/memory/spram.v
        ../../rtl/memory/bhv_spram.v
        ../../rtl/fifo/syn_fwft_fifo.v
        ../../rtl/lvds/ulink_rx.sv
        ../../sim/lvds/TB.sv
    -top
    TB

Highest level modules:
sirv_gnrl_xchecker
sirv_gnrl_dfflrs
sirv_gnrl_dfflrd
sirv_gnrl_dffl
sirv_gnrl_dffrs
sirv_gnrl_ltch
TB

Total	0 error(s),   0 warning(s)
