*design* DebussyLib (btIdent Verdi_O-2018.09-SP2)
Command arguments:
    +define+verilog
    -sverilog
    -f filelist_vlg.f
        ../../../../rtl/define/chip_define.v
        ../../../../lib/tphn28hpcpgv18.v
        ../../../../lib/tsdn28hpcpuhdb4096x128m4mw_170a_ffg0p99v0c.v
        ../../../../rtl/io/iopad.v
        ../../../../rtl/systemregfile/systemregfile.v
        ../../../../rtl/dacif/dacif.v
        ../../../../rtl/fifo/syn_fwft_fifo.v
        ../../../../rtl/dac_regfile/dac_regfile.v
        ../../../../rtl/lvds/ulink_rx.sv
        ../../../../rtl/rstgen/rst_gen_unit.v
        ../../../../rtl/rstgen/rst_sync.v
        ../../../../rtl/comm/sirv_gnrl_xchecker.v
        ../../../../rtl/comm/pulse_generator.sv
        ../../../../rtl/comm/sirv_gnrl_dffs.v
        ../../../../rtl/comm/syncer.v
        ../../../../rtl/comm/ramp_gen.v
        ../../../../rtl/memory/tsmc_dpram.v
        ../../../../rtl/memory/sram_if.sv
        ../../../../rtl/memory/sram_dmux.sv
        ../../../../rtl/memory/dpram.v
        ../../../../rtl/memory/bhv_spram.v
        ../../../../rtl/memory/spram.v
        ../../../../rtl/clk/clk_regfile.v
        ../../../../rtl/awg/awg_top.sv
        ../../../../rtl/awg/awg_ctrl.v
        ../../../../rtl/dem/DEM_PhaseSync_4008.sv
        ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_1CH.v
        ../../../../rtl/dem/DA4008_DEM_Parallel_PRBS_64CH.v
        ../../../../rtl/top/da4008_chip_top.sv
        ../../../../rtl/top/digital_top.sv
        ../../../../rtl/spi/spi_bus_decoder.sv
        ../../../../rtl/spi/spi_slave.v
        ../../../../rtl/spi/spi_pll.v
        ../../../../rtl/spi/spi_sys.v
        ../../../../model/clock_tb.v
        ../../../../model/spi_if.sv
        ../../../../model/clk_gen.v
        ../../../../model/DEM_Reverse_64CH.v
        ../../../../model/DEM_Reverse.v
        ../../../../model/reset_tb.v
        ../../../../model/DW_stream_sync.v
        ../../../../model/DW_reset_sync.v
        ../../../../model/DW_sync.v
        ../../../../model/DW_pulse_sync.v
        ../../../../sim/chip_top/TB.sv
        ../../../../rtl/define/chip_undefine.v
    -top
    TB


*Error* `include file "../define/chip_define.v" cannot be read
"../../../../rtl/io/iopad.v", 35: 

*Error* `include file "../define/chip_undefine.v" cannot be read
"../../../../rtl/io/iopad.v", 187: 

*Error* `include file "../define/chip_define.v" cannot be read
"../../../../rtl/memory/dpram.v", 2: 

*Error* `include file "../define/chip_undefine.v" cannot be read
"../../../../rtl/memory/dpram.v", 90: 

*Error* `include file "../define/chip_define.v" cannot be read
"../../../../rtl/top/da4008_chip_top.sv", 3: 

*Error* `include file "../define/chip_undefine.v" cannot be read
"../../../../rtl/top/da4008_chip_top.sv", 212: 

*Error* `include file "../define/chip_define.v" cannot be read
"../../../../rtl/top/digital_top.sv", 34: 

*Error* `include file "../define/chip_undefine.v" cannot be read
"../../../../rtl/top/digital_top.sv", 528: 

*Error* `include file "../../rtl/define/chip_define.v" cannot be read
"../../../../sim/chip_top/TB.sv", 1: 

*Error* `include file "../../model/SPI_DRIVER.sv" cannot be read
"../../../../sim/chip_top/TB.sv", 3: 

*Error* `include file "../../model/LVDS_DRIVER.sv" cannot be read
"../../../../sim/chip_top/TB.sv", 5: 

*Error* failed to find symbol 'my_drv'
"../../../../sim/chip_top/TB.sv", 81: 

*Error* failed to find symbol 'lvds_drv'
"../../../../sim/chip_top/TB.sv", 82: 
Highest level modules:
PCLAMP_G
PCLAMPC_H_G
PCLAMPC_V_G
PDB3A_H_G
PDB3A_V_G
PDB3AC_H_G
PDB3AC_V_G
PDDW04DGZ_H_G
PDDW04DGZ_V_G
PDDW04SDGZ_H_G
PDDW08DGZ_H_G
PDDW08DGZ_V_G
PDDW08SDGZ_H_G
PDDW08SDGZ_V_G
PDDW12DGZ_H_G
PDDW12DGZ_V_G
PDDW12SDGZ_H_G
PDDW12SDGZ_V_G
PDDW16DGZ_H_G
PDDW16DGZ_V_G
PDDW16SDGZ_H_G
PDDW16SDGZ_V_G
PDUW04DGZ_H_G
PDUW04DGZ_V_G
PDUW04SDGZ_H_G
PDUW08DGZ_H_G
PDUW08DGZ_V_G
PDUW08SDGZ_H_G
PDUW12DGZ_H_G
PDUW12DGZ_V_G
PDUW12SDGZ_H_G
PDUW12SDGZ_V_G
PDUW16DGZ_H_G
PDUW16DGZ_V_G
PDUW16SDGZ_H_G
PDUW16SDGZ_V_G
PDXOEDG_H_G
PDXOEDG_V_G
PENDCAP_G
PENDCAPA_G
PRCUT_G
PRCUTA_G
PRDW08DGZ_H_G
PRDW08DGZ_V_G
PRDW08SDGZ_H_G
PRDW08SDGZ_V_G
PRDW12DGZ_H_G
PRDW12DGZ_V_G
PRDW12SDGZ_H_G
PRDW12SDGZ_V_G
PRDW16DGZ_H_G
PRDW16DGZ_V_G
PRDW16SDGZ_H_G
PRDW16SDGZ_V_G
PRUW08DGZ_H_G
PRUW08DGZ_V_G
PRUW08SDGZ_H_G
PRUW08SDGZ_V_G
PRUW12DGZ_H_G
PRUW12DGZ_V_G
PRUW12SDGZ_H_G
PRUW12SDGZ_V_G
PRUW16DGZ_H_G
PRUW16DGZ_V_G
PRUW16SDGZ_H_G
PRUW16SDGZ_V_G
PVDD1A_H_G
PVDD1A_V_G
PVDD1AC_H_G
PVDD1AC_V_G
PVDD1ANA_H_G
PVDD1ANA_V_G
PVDD1DGZ_H_G
PVDD1DGZ_V_G
PVDD2ANA_H_G
PVDD2ANA_V_G
PVDD2DGZ_H_G
PVDD2DGZ_V_G
PVDD2POC_H_G
PVDD2POC_V_G
PVDD3A_H_G
PVDD3A_V_G
PVDD3AC_H_G
PVDD3AC_V_G
PVSS1A_H_G
PVSS1A_V_G
PVSS1AC_H_G
PVSS1AC_V_G
PVSS1ANA_H_G
PVSS1ANA_V_G
PVSS1DGZ_H_G
PVSS1DGZ_V_G
PVSS2A_H_G
PVSS2A_V_G
PVSS2AC_H_G
PVSS2AC_V_G
PVSS2ANA_H_G
PVSS2ANA_V_G
PVSS2DGZ_H_G
PVSS2DGZ_V_G
PVSS3A_H_G
PVSS3A_V_G
PVSS3AC_H_G
PVSS3AC_V_G
PVSS3DGZ_H_G
PVSS3DGZ_V_G
sirv_gnrl_xchecker
sirv_gnrl_dffl
sirv_gnrl_ltch
clk_gen
reset_tb
TB


*Error* failed to find identifier lvds_drv
"../../../../sim/chip_top/TB.sv", 89: 

*Error* failed to find identifier lvds_drv.new
"../../../../sim/chip_top/TB.sv", 89: 

*Error* failed to find identifier lvds_drv.drv_if
"../../../../sim/chip_top/TB.sv", 91: 

*Error* failed to find identifier my_drv
"../../../../sim/chip_top/TB.sv", 94: 

*Error* failed to find identifier my_drv.new
"../../../../sim/chip_top/TB.sv", 94: 

*Error* failed to find identifier my_drv.file_path
"../../../../sim/chip_top/TB.sv", 95: 

*Error* failed to find identifier my_drv.itf
"../../../../sim/chip_top/TB.sv", 96: 

*Error* failed to find identifier lvds_drv.train_count
"../../../../sim/chip_top/TB.sv", 102: 

*Error* failed to find identifier lvds_drv.send_training
"../../../../sim/chip_top/TB.sv", 103: 

*Error* failed to find identifier lvds_drv.scrambler_en
"../../../../sim/chip_top/TB.sv", 104: 

*Error* failed to find identifier lvds_drv.send_frame_from_file
"../../../../sim/chip_top/TB.sv", 105: 

*Error* failed to find identifier my_drv.do_drive
"../../../../sim/chip_top/TB.sv", 108: 

*Error* failed to find identifier my_drv.do_drive
"../../../../sim/chip_top/TB.sv", 120: 

*Error* failed to find identifier my_drv.do_drive
"../../../../sim/chip_top/TB.sv", 131: 

*Error* failed to find identifier lvds_bus.data
"../../../../sim/chip_top/TB.sv", 218: 

*Error* failed to find identifier lvds_bus.valid
"../../../../sim/chip_top/TB.sv", 219: 

*Error* failed to find identifier lvds_bus.clk
"../../../../sim/chip_top/TB.sv", 220: 

*Error* view lvds_if is not defined for instance lvds_bus
"../../../../sim/chip_top/TB.sv", 69: 
Total	31 error(s),   0 warning(s)
