//+FHDR--------------------------------------------------------------------------------------------------------
//  Company: 
//-----------------------------------------------------------------------------------------------------------------
//  File Name             :    digital_top.v
//  Department            :    
//  Author                :    pwy
//  Author's Tel          :     
//-----------------------------------------------------------------------------------------------------------------
//  Relese History
//  Version     Date            Author          Description
//  1.2         2024-04-16       pwy           XYZ control the top-level module
//-----------------------------------------------------------------------------------------------------------------
//  Keywords            :       
//          
//-----------------------------------------------------------------------------------------------------------------
//  Parameter
//
//-----------------------------------------------------------------------------------------------------------------
//  Purpose                 :
//                      
//-----------------------------------------------------------------------------------------------------------------
//  Target Device:        
//  Tool versions:        
//-----------------------------------------------------------------------------------------------------------------
//  Reuse Issues
//  Reset Strategy: 
//  Clock Domains: 
//  Critical Timing:
//  Asynchronous I/F:
//  Synthesizable (y/n): 
//  Other:
//-FHDR-------------------------------------------------------------------------------------------------------- 

`include "../define/chip_define.v"

module digital_top ( 
  //system port
   input          clk               // System Main Clock
  ,input          rst_n             // Spi Reset active low
  ,input          sync_in
  ,input          sync_out
  //spi port 
  ,input  [4  :0] cfgid                   
  ,input          sclk           // Spi Clock
  ,input          csn            // Spi Chip Select active low
  ,input          mosi           // Spi Mosi
  ,output         miso           // Spi Miso
  ,output         oen
  //irq
  ,output         irq
  //wave port
  ,output [7  :0] wave_data_out [63:0]
  ,output         wave_data_valid
  //lvds rx
  ,input  [3  :0]  lvds_data
  ,input  [0  :0]  lvds_valid
  ,input  [0  :0]  lvds_clk
  ,output [2  :0]  phase_tap  
  //DAC Cfg Port
  ,output [3  :0] Rterm           
  ,output         PrbsEn          
  ,output [14 :0] Set [63:0] 
  ,output [2  :0] CasAddr
  ,output [2  :0] CasDw
  ,output [9  :0] IMainCtrl  
  ,output [3  :0] IBleedCtrl
  ,output [3  :0] ICkCml
  ,output [31 :0] CurRsv0
  ,output [31 :0] CurRsv1
  //CLK Cfg Port
  ,output [0  :0] CcalRstn
  ,output [3  :0] EnAllP
  ,output [0  :0] DccEn
  ,output [0  :0] CasGateCkCtrl
  ,output [0  :0] SpiEnPi
  ,output [0  :0] SpiEnQec
  ,output [0  :0] SpiEnDcc
  ,output [4  :0] SpiQecCtrlIp 
  ,output [4  :0] SpiQecCtrlIn 
  ,output [4  :0] SpiQecCtrlQp 
  ,output [4  :0] SpiQecCtrlQn
  ,output [5  :0] SpiDccCtrlIup 
  ,output [5  :0] SpiDccCtrlIdn 
  ,output [5  :0] SpiDccCtrlQup 
  ,output [5  :0] SpiDccCtrlQdn
  ,output [7  :0] SpiSiqNOut 
  ,output [7  :0] SpiSiqPOut 
  ,output [3  :0] SpiSiPOut 
  ,output [3  :0] SpiSqPOut 
  ,output [2  :0] CrtlCrossOverN 
  ,output [2  :0] CrtlCrossOverP
  ,output [31 :0] CcalRsv0
  ,output [31 :0] CcalRsv1
  ,output [3  :0] SelCk10GDig 
  ,output [3  :0] SelCk2p5GDig 
  ,output [8  :0] SelCk625MDig 
  ,output [15 :0] P2sDataEn 
  ,output [15 :0] P2sEnAllP
  ,output [15 :0] EnPiP
  ,output [15 :0] CkDivRstn
  ,output [31 :0] p2srsv0
  ,output [31 :0] p2srsv1
  ,output [15 :0] CkRxSw
  ,output [15 :0] RstnCk
  ,output [15 :0] CtrlZin
);

//------------------------------spi_slave instantiation start----------------------------------
// spi_slave
//---------------------------------------------------------------------------------------------
sram_if#(25,32)  mst(clk);
sram_if#(20,32)  slv[3:0](clk);
//connect pll
wire [31 :0] clk_wrdata ;  
wire         clk_wren   ;        
wire [7  :0] clk_rwaddr ;        
wire         clk_rden   ;        
wire [31 :0] clk_rddata ;
//connect system        
wire [31 :0] sys_wrdata ; 
wire         sys_wren   ;        
wire [24 :0] sys_rwaddr ;        
wire         sys_rden   ;        
wire [31 :0] sys_rddata ;

wire pll_rstn_o;

assign mst.wben = 4'hf;
  
spi_slave U_spi_slave                       (
   .clk                                     ( clk                                     )               
  ,.rst_n                                   ( pll_rstn_o                              )
  ,.cfgid                                   ( cfgid                                   )
  ,.sclk                                    ( sclk                                    )
  ,.csn                                     ( csn                                     )
  ,.mosi                                    ( mosi                                    )
  ,.miso                                    ( miso                                    )
  ,.oen                                     ( oen                                     )
  ,.pll_wrdata                              ( clk_wrdata                              )
  ,.pll_wren                                ( clk_wren                                )
  ,.pll_rwaddr                              ( clk_rwaddr                              )
  ,.pll_rden                                ( clk_rden                                )
  ,.pll_rddata                              ( clk_rddata                              )
  ,.sys_wrdata                              ( mst.din                                 )
  ,.sys_wren                                ( mst.wren                                )
  ,.sys_rwaddr                              ( mst.addr                                )
  ,.sys_rden                                ( mst.rden                                )
  ,.sys_rddata                              ( mst.dout                                )
);
//---------------------------------------------------------------------------------------------
// spi_slave
//------------------------------spi_slave instantiation end------------------------------------

spi_bus_decoder                            #(
   .SLVNUM                                  ( `SLVNUM                                 )
  ,.SPIBUS_CMD_REG                          ( `SPIBUS_CMD_REG                         )
  ,.SPIBUS_OUT_REG                          ( `SPIBUS_OUT_REG                         )
  ) U_spi_bus_decoder                       (                                         
   .clk                                     ( clk                                     )
  ,.rst_n                                   ( pll_rstn_o                              )
  ,.mst                                     ( mst                                     )
  ,.slv                                     ( slv                                     )
  );
//---------------------------------------------------------------------------------------------
// spi_bus_decoder
//------------------------------spi_bus_decoder instantiation end------------------------------

//-----------------------------system_regfile instantiation start------------------------------
// system_regfile as slave device 0
//---------------------------------------------------------------------------------------------
wire [2  :0] awg_status       ;
wire         awg_busy         ;
wire         sys_soft_rstn    ;
wire         dout_sel         ;
wire [15 :0] sync_delay       ;
wire         int_sync         ;
wire         int_sync_en      ;
wire         sync_oen         ;
wire         ramp_en          ; 
wire [31 :0] ramp_ifs         ;
wire [7  :0] ramp_step        ;
wire         ramp_fixed       ;
wire [7  :0] ramp_fixed_value ;
//LVDS
wire          force_train      ;       
wire          tap_force        ; 
wire  [2  :0] tap_step         ;
wire  [2  :0] tap_adj_mask     ;
wire  [19 :0] train_threshold  ;
wire          descram_en       ;
wire          always_on        ;
                               ;
wire          link_down        ;
wire          train_ready      ;   
wire          crc_error        ; 
wire          phase_adj_req    ;                 
wire [31 :0]  frame_success_cnt;   
wire [31 :0]  crc_err_cnt      ; 
wire          prefilling       ;
wire [31 :0]  train_status     ;
wire [31 :0]  frame_status     ;

systemregfile U_systemregfile             (
   .clk                                     ( clk                                     )            
  ,.rst_n                                   ( pll_rstn_o                              )
  ,.wrdata                                  ( slv[0].din                              )
  ,.wren                                    ( slv[0].wren                             )
  ,.rwaddr                                  ( slv[0].addr[15:0]                       )
  ,.rden                                    ( slv[0].rden                             )
  ,.rddata                                  ( slv[0].dout                             )
  ,.irq                                     ( irq                                     )
  ,.cmd_fifo_full                           ( cmd_fifo_full                           )
  ,.cmd_fifo_empty                          ( cmd_fifo_empty                          )
  ,.awg_status                              ( awg_status                              )
  ,.awg_busy                                ( awg_busy                                )
  ,.sys_soft_rstn                           ( sys_soft_rstn                           )
  ,.dout_sel                                ( dout_sel                                )
  ,.sync_delay                              ( sync_delay                              )
  ,.int_sync                                ( int_sync                                )
  ,.int_sync_en                             ( int_sync_en                             )
  ,.sync_oen                                ( sync_oen                                )
  ,.ramp_en                                 ( ramp_en                                 )
  ,.ramp_ifs                                ( ramp_ifs                                )
  ,.ramp_step                               ( ramp_step                               )
  ,.ramp_fixed                              ( ramp_fixed                              )
  ,.ramp_fixed_value                        ( ramp_fixed_value                        )
  ,.force_train                             ( force_train                             )         
  ,.tap_force                               ( tap_force                               )
  ,.tap_step                                ( tap_step                                )
  ,.tap_adj_mask                            ( tap_adj_mask                            )
  ,.train_threshold                         ( train_threshold                         )
  ,.descram_en                              ( descram_en                              )
  ,.always_on                               ( always_on                               )
  ,.link_down                               ( link_down                               )
  ,.train_ready                             ( train_ready                             )
  ,.crc_error                               ( crc_error                               )
  ,.phase_adj_req                           ( phase_adj_req                           )
  ,.phase_tap                               ( phase_tap                               )
  ,.frame_success_cnt                       ( frame_success_cnt                       )
  ,.crc_err_cnt                             ( crc_err_cnt                             )
  ,.prefilling                              ( prefilling                              )
  ,.train_status                            ( train_status                            )
  ,.frame_status                            ( frame_status                            )
);


//---------------------------------------------------------------------------------------------
// system_regfile
//------------------------------system_regfile instantiation end-------------------------------

//---------------------------------------------------------------------------------------------
// rst_gen_unit instantiation start
//---------------------------------------------------------------------------------------------
wire ch0_rstn_o;

rst_gen_unit U_rst_gen_unit                 (
   .async_rstn_i                            ( rst_n                                   )        
  ,.por_rstn_i                              ( 1'b1                                    )
  ,.sys_soft_resetn_i                       ( sys_soft_rstn                           )
  ,.ch0_soft_rstn_i                         ( 1'b1                                    )
  ,.ch1_soft_rstn_i                         ( 1'b1                                    )
  ,.ch2_soft_rstn_i                         ( 1'b1                                    )
  ,.ch3_soft_rstn_i                         ( 1'b1                                    )
  ,.clk                                     ( clk                                     )
  ,.ch0_rstn_o                              ( ch0_rstn_o                              )
  ,.ch1_rstn_o                              (                                         )
  ,.ch2_rstn_o                              (                                         )
  ,.ch3_rstn_o                              (                                         )
  ,.pll_rstn_o                              ( pll_rstn_o                              )
);

//---------------------------------------------------------------------------------------------
// DW_stream_sync  instantiation start
//---------------------------------------------------------------------------------------------
wire         dst_valid         ;
wire [3  :0] dst_data          ;
wire         prefill_d         ;
DW_stream_sync                             #(
   .width                                   ( 4                                       )
  ,.depth                                   ( 32                                      )
  ,.prefill_lvl                             ( 16                                      )
  ,.tst_mode                                ( 0                                       )
  ,.verif_en                                ( 0                                       )
) u_dw_stream_sync                          (
   .clk_s                                   ( lvds_clk                                )
  ,.rst_s_n                                 ( pll_rstn_o                              )
  ,.init_s_n                                ( 1'b1                                    )
  ,.clr_s                                   ( 1'b0                                    )
  ,.send_s                                  ( 1'b1                                    )
  ,.data_s                                  ( lvds_data                               )
  ,.clr_sync_s                              (                                         )
  ,.clr_in_prog_s                           (                                         )
  ,.clr_cmplt_s                             (                                         )
  ,.clk_d                                   ( clk                                     )
  ,.rst_d_n                                 ( pll_rstn_o                              )
  ,.init_d_n                                ( 1'b1                                    )
  ,.clr_d                                   ( 1'b0                                    )
  ,.prefill_d                               ( prefill_d                               )
  ,.clr_in_prog_d                           (                                         )
  ,.clr_sync_d                              (                                         )
  ,.clr_cmplt_d                             (                                         )
  ,.data_avail_d                            ( dst_valid                               )
  ,.data_d                                  ( dst_data                                )
  ,.prefilling_d                            ( prefilling                              )
  ,.test                                    ( 1'b0                                    )
);

//---------------------------------------------------------------------------------------------
// lvds_rx_4ch instantiation start
//---------------------------------------------------------------------------------------------
parameter FIFO_DEPTH       = 64;
parameter SCRAMBLER_SEED   = 32'hFFFFFFFF;

wire [511:0] wave_awrdata      ; 
wire [0  :0] wave_awren        ;
wire [12 :0] wave_arwaddr      ;  
wire [63 :0] wave_awrmask      ; 
    
ulink_rx                                   #(
  .FIFO_DEPTH                               ( FIFO_DEPTH                              )
 ,.SCRAMBLER_SEED                           ( SCRAMBLER_SEED                          )
) dut                                       (                                         
   .clk                                     ( clk                                     )
  ,.rst_n                                   ( pll_rstn_o                              )
  ,.serial_in                               ( dst_data                                )
  ,.patn_count                              ( train_threshold                         )
  ,.tap_step                                ( tap_step                                )
  ,.descram_en                              ( descram_en                              )   
  ,.link_down                               ( link_down                               )
  ,.delay_tap                               ( phase_tap                               )
  ,.wr_addr                                 ( wave_arwaddr                            )
  ,.wr_data                                 ( wave_awrdata                            )
  ,.wr_en                                   ( wave_awren                              )
  ,.byte_mask                               ( wave_awrmask                            )
  ,.crc_error                               ( crc_error                               )
  ,.tap_adj_mask                            ( tap_adj_mask                            )
  ,.tap_force                               ( tap_force                               )
  ,.tap_adj_req                             ( tap_adj_req                             )
  ,.frame_done                              ( frame_done                              )
  ,.train_status                            ( train_status                            )
  ,.frame_status                            ( frame_status                            )
  ,.always_on                               ( always_on                               )
  ,.prefilling                              ( prefilling                              )
  ,.prefill_start                           ( prefill_d                               )
  ,.train_ready                             ( train_ready                             )
  ,.force_train                             ( force_train                             )
);


//---------------------------------------------------------------------------------------------
// sync_int
//------------------------------sync_int instantiation start-----------------------------------

wire sync_int;
wire sync_pulse;
syncer #(1, 2) sync_in_syncer (clk, pll_rstn_o, sync_in, sync_int); 

sirv_gnrl_dffr #(1) sync_out_dffr (sync_pulse & sync_oen, sync_out, clk, rst_n);
assign sync_out = sync_pulse;
//---------------------------------------------------------------------------------------------
// Synchronization Signal Delay Adjustment Module instantiation start
//---------------------------------------------------------------------------------------------

wire sync_src = (int_sync | sync_int) & int_sync_en;

pulse_generator pulse_inst_sync              (
   .clk                                      ( clk                                      )
  ,.rst_n                                    ( pll_rstn_o                               )
  ,.pulse_en                                 ( sync_src                                 )
  ,.delay                                    ( sync_delay                               )
  ,.width                                    ( 16'd1                                    )
  ,.inv_en                                   ( 1'b0                                     )
  ,.pulse                                    ( sync_pulse                               )
);

//---------------------------------------------------------------------------------------------
// sync_int
//------------------------------sync_int instantiation end-------------------------------------

//---------------------------------------------------------------------------------------------
// awg_top instantiation start
//---------------------------------------------------------------------------------------------
wire [511:0] wave_data_out_bank  ;

wire [7  :0] awg_data_out [63:0] ;
wire         awg_data_valid      ;
  
awg_top U_awg_top (
   .clk                                     ( clk                                    )
  ,.rst_n                                   ( ch0_rstn_o                             )
  ,.start                                   ( sync_pulse                             )
  ,.wave_awrdata                            ( wave_awrdata                           )    
  ,.wave_awren                              ( wave_awren                             )  
  ,.wave_arwaddr                            ( wave_arwaddr                           ) 
  ,.wave_awrmask                            ( wave_awrmask                           )
  ,.wave_bwrdata                            ( slv[2].din                             )    
  ,.wave_bwren                              ( slv[2].wren                            )  
  ,.wave_brwaddr                            ( slv[2].addr[18:0]                      )  
  ,.wave_brden                              ( slv[2].rden                            )  
  ,.wave_brddata                            ( slv[2].dout                            )  
  ,.cmd_fifo_bwrdata                        ( slv[1].din                             )  
  ,.cmd_fifo_bwren                          ( slv[1].wren                            )  
  ,.cmd_fifo_brwaddr                        ( slv[1].addr[7 :0]                      )  
  ,.cmd_fifo_brden                          ( slv[1].rden                            )  
  ,.cmd_fifo_brddata                        ( slv[1].dout                            )     
  ,.wave_data_out                           ( wave_data_out_bank                     )    
  ,.wave_valid_out                          ( awg_data_valid                         ) 
  ,.cmd_fifo_empty                          ( cmd_fifo_empty                         )
  ,.cmd_fifo_full                           ( cmd_fifo_full                          )
  ,.status                                  ( awg_status                             )  
  ,.wave_busy                               ( awg_busy                               ) 
  );

genvar i;
generate
  for(i = 0; i < 64; i++) begin
    assign awg_data_out[i] = wave_data_out_bank[8*i +: 8];
  end
endgenerate

//---------------------------------------------------------------------------------------------
// ramp_gen instantiation start
//---------------------------------------------------------------------------------------------
wire [7 :0] ramp_data [63:0];
wire        ramp_vld;
ramp_gen U_ramp_gen                         (
  //system port
   .clk                                     ( clk                                       )    
  ,.rst_n                                   ( rst_n                                     )
  ,.dac_mode_sel                            ( 2'b10                                     )
  ,.cen                                     ( ramp_en                                   )
  ,.step                                    ( ramp_step                                 )
  ,.ifs                                     ( ramp_ifs                                  )
  ,.fixed                                   ( ramp_fixed                                )
  ,.fixed_value                             ( ramp_fixed_value                          )
  ,.ramp                                    ( ramp_data                                 )
  ,.ramp_vld                                ( ramp_vld                                  )
);


wire [7  :0] wave_data_out_i [63:0] = dout_sel ? ramp_data : awg_data_out   ; 
wire wave_data_valid_i              = dout_sel ? ramp_vld  : awg_data_valid ;

//---------------------------------------------------------------------------------------------
// dacif instantiation start
//---------------------------------------------------------------------------------------------
dacif dacif_inst                            (
   .clk                                     ( clk                                       )
  ,.rstn                                    ( rst_n                                     )           
  ,.din_vld                                 ( wave_data_valid_i                         )                  
  ,.din                                     ( wave_data_out_i                           )
  ,.dout_vld                                ( wave_data_valid                           )  
  ,.dout                                    ( wave_data_out                             )
); 

//---------------------------------------------------------------------------------------------
// dac_regfile instantiation start
//---------------------------------------------------------------------------------------------
dac_regfile U_dac_regfile                   (
   .clk                                     ( clk                                     )
  ,.rstn                                    ( ch0_rstn_o                              )
  ,.wrdata                                  ( slv[3].din                              )
  ,.wren                                    ( slv[3].wren                             )
  ,.rwaddr                                  ( slv[3].addr[15:0]                       )
  ,.rden                                    ( slv[3].rden                             )
  ,.rddata                                  ( slv[3].dout                             )
  ,.Rterm                                   ( Rterm                                   )
  ,.PrbsEn                                  ( PrbsEn                                  )
  ,.Set                                     ( Set                                     )
  ,.CasAddr                                 ( CasAddr                                 )
  ,.CasDw                                   ( CasDw                                   )
  ,.IMainCtrl                               ( IMainCtrl                               )
  ,.IBleedCtrl                              ( IBleedCtrl                              )
  ,.ICkCml                                  ( ICkCml                                  )
  ,.CurRsv0                                 ( CurRsv0                                 )
  ,.CurRsv1                                 ( CurRsv1                                 )
);

//---------------------------------------------------------------------------------------------
// clk_regfile instantiation start
//---------------------------------------------------------------------------------------------
clk_regfile U_clk_regfile                   (
   .clk                                     ( clk                                     )             
  ,.rstn                                    ( pll_rstn_o                              )
  ,.wrdata                                  ( clk_wrdata                              )
  ,.wren                                    ( clk_wren                                )
  ,.rwaddr                                  ( clk_rwaddr                              )
  ,.rden                                    ( clk_rden                                )
  ,.rddata                                  ( clk_rddata                              )
  ,.CcalRstn                                ( CcalRstn                                )
  ,.EnAllP                                  ( EnAllP                                  )
  ,.DccEn                                   ( DccEn                                   )
  ,.CasGateCkCtrl                           ( CasGateCkCtrl                           )
  ,.SpiEnPi                                 ( SpiEnPi                                 )
  ,.SpiEnQec                                ( SpiEnQec                                )
  ,.SpiEnDcc                                ( SpiEnDcc                                )
  ,.SpiQecCtrlIp                            ( SpiQecCtrlIp                            )
  ,.SpiQecCtrlIn                            ( SpiQecCtrlIn                            )
  ,.SpiQecCtrlQp                            ( SpiQecCtrlQp                            )
  ,.SpiQecCtrlQn                            ( SpiQecCtrlQn                            )
  ,.SpiDccCtrlIup                           ( SpiDccCtrlIup                           )
  ,.SpiDccCtrlIdn                           ( SpiDccCtrlIdn                           )
  ,.SpiDccCtrlQup                           ( SpiDccCtrlQup                           )
  ,.SpiDccCtrlQdn                           ( SpiDccCtrlQdn                           )
  ,.SpiSiqNOut                              ( SpiSiqNOut                              )
  ,.SpiSiqPOut                              ( SpiSiqPOut                              )
  ,.SpiSiPOut                               ( SpiSiPOut                               )
  ,.SpiSqPOut                               ( SpiSqPOut                               )
  ,.CrtlCrossOverN                          ( CrtlCrossOverN                          )
  ,.CrtlCrossOverP                          ( CrtlCrossOverP                          )
  ,.CcalRsv0                                ( CcalRsv0                                )
  ,.CcalRsv1                                ( CcalRsv1                                )
  ,.SelCk10GDig                             ( SelCk10GDig                             )
  ,.SelCk2p5GDig                            ( SelCk2p5GDig                            )
  ,.SelCk625MDig                            ( SelCk625MDig                            )
  ,.P2sDataEn                               ( P2sDataEn                               )
  ,.P2sEnAllP                               ( P2sEnAllP                               )
  ,.EnPiP                                   ( EnPiP                                   )
  ,.CkDivRstn                               ( CkDivRstn                               )
  ,.p2srsv0                                 ( p2srsv0                                 )
  ,.p2srsv1                                 ( p2srsv1                                 )
  ,.CkRxSw                                  ( CkRxSw                                  )
  ,.RstnCk                                  ( RstnCk                                  )
  ,.CtrlZin                                 ( CtrlZin                                 )
);

endmodule
`include "../define/chip_undefine.v"

