//`define FPGA_XIL

//`define SMIC_IC


`define BEHAVIOUR_SIM


module spram #(
parameter  width =16,
parameter  depth =1024

)(
        clka,
        ena,
        dina,
        addra,

        clkb,
    enb,
        doutb,
        addrb   
);
///////////////////////////////////////////////////////
//Function
///////////////////////////////////////////////////////
function integer clog2(input integer depth);
begin
        for(clog2=0;depth>0;clog2=clog2+1)
                depth =depth>>1;
end
endfunction

localparam aw = clog2(depth-1);

///////////////////////////////////////////////////////
//Input declaration
///////////////////////////////////////////////////////
input              clka;
input              ena;
input  [width-1:0] dina;
input  [aw-1:0]    addra;

input              clkb;
input              enb;
output [width-1:0] doutb;
input  [aw-1:0]    addrb;

///////////////////////////////////////////////////////
//SRAM
///////////////////////////////////////////////////////
`ifdef BEHAVIOUR_SIM
bhv_spram #(
        .width (width   ),
        .depth (depth   )
)bhv_spram(
        .clka                           (clka                   ),
        .ena                            (ena            ),
        .dina                           (dina           ),
        .addra                          (addra          ),
        .clkb                           (clkb                   ),
        .enb                            (enb            ),
        .doutb                          (doutb          ),
        .addrb                          (addrb          )
);

`elsif XINLINX_FPGA
xil_spram #(
    .dw         (width     ),
    .depth  (depth     )
)xil_spram(
        .wrclk                     (clka                    ),
        .wren                      (ena             ),
        .wrdata                    (dina            ),
        .wraddr            (addra           ),
        .rdclk                     (clkb            ),
        .rden              (enb             ),
        .rddata                    (doutb           ),
        .rdaddr                    (addrb           )
    );
`elsif SMIC_IC
smic_spram #(
	.width (width),
	.depth (depth)
)smic_spram(
  		.CLKB					(clka			),
  		.CENB					(ena			),
  		.AB						(addra			),
  		.DB						(dina		    ),

  		.CLKA					(clkb			),
  		.CENA					(enb			),
  		.AA						(addrb			),
  		.QA						(doutb			)
);   
`endif
endmodule

//`undef FPGA_XIL


