`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2026/02/28 19:57:30
// Design Name: 
// Module Name: dac_regfile
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// Revision Date: 2026/02/28 19:57:30
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

// -----------------------------------------------------------
// -- Register address offset macros
// -----------------------------------------------------------
//Prbs_en Ctrl Register

`define CCALRSTNR           8'h00
`define CCLKDCCENR          8'h04
`define CASCLKCTR           8'h08
`define CCALDCCQECPIR       8'h0C
`define CCALQECCTR1         8'h10
`define CCALDCCCTR1         8'h14
`define CCALPICTR           8'h18
`define CCALCROSSCTR        8'h1C
`define CCALRSVR0           8'h20
`define CCALRSVR1           8'h24
`define SELCK10GDR          8'h28
`define SELCK2P5GDR         8'h2C
`define SELCK625MDR         8'h30
`define P2SDATAENR          8'h34
`define ENALLPR             8'h38
`define ENPIPR              8'h3C
`define CLKDIVRSTNR         8'h40
`define P2SRSVR0            8'h44
`define P2SRSVR1            8'h48
`define CKRXSWR             8'h4C  
`define RSTCKR              8'h50
`define CTRLZINR            8'h54


module clk_regfile (
  //system port
   input          clk             // System Main Clock
  ,input          rstn            // Spi Reset active low
  //rw op port
  ,input  [31 :0] wrdata          // write data
  ,input          wren            // write enable
  ,input  [7  :0] rwaddr          // read & write address
  ,input          rden            // read enable
  ,output [31 :0] rddata          // read data
  ,output [0  :0] CcalRstn
  ,output [3  :0] EnAllP
  ,output [0  :0] DccEn
  ,output [0  :0] CasGateCkCtrl
  ,output [0  :0] SpiEnPi
  ,output [0  :0] SpiEnQec
  ,output [0  :0] SpiEnDcc
  ,output [4  :0] SpiQecCtrlIp 
  ,output [4  :0] SpiQecCtrlIn 
  ,output [4  :0] SpiQecCtrlQp 
  ,output [4  :0] SpiQecCtrlQn
  ,output [5  :0] SpiDccCtrlIup 
  ,output [5  :0] SpiDccCtrlIdn 
  ,output [5  :0] SpiDccCtrlQup 
  ,output [5  :0] SpiDccCtrlQdn
  ,output [7  :0] SpiSiqNOut 
  ,output [7  :0] SpiSiqPOut 
  ,output [3  :0] SpiSiPOut 
  ,output [3  :0] SpiSqPOut 
  ,output [2  :0] CrtlCrossOverN 
  ,output [2  :0] CrtlCrossOverP
  ,output [31 :0] CcalRsv0
  ,output [31 :0] CcalRsv1
  ,output [3  :0] SelCk10GDig 
  ,output [3  :0] SelCk2p5GDig 
  ,output [8  :0] SelCk625MDig 
  ,output [15 :0] P2sDataEn 
  ,output [15 :0] P2sEnAllP
  ,output [15 :0] EnPiP
  ,output [15 :0] CkDivRstn
  ,output [31 :0] p2srsv0
  ,output [31 :0] p2srsv1
  ,output [15 :0] CkRxSw
  ,output [15 :0] RstnCk
  ,output [15 :0] CtrlZin
);

localparam L = 1'b0,
           H = 1'b1;
		   
// ------------------------------------------------------
// -- Register Default Vaule
// ------------------------------------------------------
wire  [0 :0] ccalrstnrdft       = 1'b0                                      ; // CCALRSTNR     16'h0000
wire  [4 :0] cclkdccenrdft      = 5'b0                                      ; // CCLKDCCENR    16'h0004
wire  [0 :0] casclkctrdft       = 1'b1                                      ; // CASCLKCTR     16'h0008
wire  [2 :0] ccaldccqecpirdft   = 3'b0                                      ; // CCALDCCQECPIR 16'h000C
wire  [19:0] ccalqecctr1dft     = {5'b10001,5'b10001,5'b10000,5'b10000}     ; // CCALQECCTR1   16'h0010
wire  [23:0] ccaldccctr1dft     = {6'b111111,6'b000000,6'b111111,6'b000000} ; // CCALDCCCTR1   16'h0014
wire  [23:0] ccalpictrdft       = {8'b11111111,8'b00000000,4'b0011,4'b0000} ; // CCALPICTR     16'h0018
wire  [5 :0] ccalcrossctrdft    = {3'b100,3'b110}                           ; // CCALCROSSCTR  16'h001C
wire  [31:0] ccalrsvr0dft       = 32'h0                                     ; // CCALRSVR0     16'h0020
wire  [31:0] ccalrsvr1dft       = 32'h0                                     ; // CCALRSVR1     16'h0024
wire  [3 :0] selck10gdrdft      = 4'b0001                                   ; // SELCK10GDR    16'h0028
wire  [3 :0] selck2p5gdrdft     = 4'b0010                                   ; // SELCK2P5GDR   16'h002C
wire  [8 :0] selck625mdrdft     = 9'b100001010                              ; // SELCK625MDR   16'h0030
wire  [15:0] p2sdataenrdft      = 16'h1                                     ; // P2SDATAENR    16'h0034
wire  [15:0] enallprdft         = 16'h1                                     ; // ENALLPR       16'h0038
wire  [15:0] enpiprdft          = 16'h1                                     ; // ENPIPR        16'h003C
wire  [15:0] clkdivrstnrdft     = 16'h1                                     ; // CLKDIVRSTNR   16'h0040
wire  [31:0] p2srsvr0dft        = 32'h0                                     ; // P2SRSVR0      16'h0044
wire  [31:0] p2srsvr1dft        = 32'h0                                     ; // P2SRSVR1      16'h0048
wire  [15:0] ckrxswrdft         = 16'h1                                     ; // CKRXSWR       16'h004C
wire  [15:0] rstckrdft          = 16'h1                                     ; // RSTCKR        16'h0050
wire  [15:0] ctrzinrdft         = 16'h1                                     ; // CTRLZINR      16'h0054
		   
// ------------------------------------------------------
// -- Register enable (select) wires
// ------------------------------------------------------
wire         ccalrstnren          ;  // CCALRSTNR       Enable
wire         cclkdccenren         ;  // CCLKDCCEN       Enable
wire         casclkctren          ;  // CASCLKCTR       Enable
wire         ccaldccqecpiren      ;  // CCALDCCQECPIR   Enable
wire         ccalqecctr1en        ;  // CCALQECCTR1     Enable
wire         ccaldccctr1en        ;  // CCALDCCCTR1     Enable
wire         ccalpictren          ;  // CCALPICTR       Enable
wire         ccalcrossctren       ;  // CCALCROSSCTR    Enable
wire         ccalrsvr0en          ;  // CCALRSVR0       Enable
wire         ccalrsvr1en          ;  // CCALRSVR1       Enable
wire         selck10gdren         ;  // SELCK10GDR      Enable
wire         selck2p5gdren        ;  // SELCK2P5GDR     Enable
wire         selck625mdren        ;  // SELCK625MDR     Enable
wire         p2sdataenren         ;  // P2SDATAENR      Enable
wire         enallpren            ;  // ENALLPR         Enable
wire         enpipren             ;  // ENPIPR          Enable
wire         clkdivrstnren        ;  // CLKDIVRSTNR     Enable
wire         p2srsvr0en           ;  // P2SRSVR0        Enable
wire         p2srsvr1en           ;  // P2SRSVR1        Enable
wire         ckrxswren            ;  // CKRXSWR         Enable
wire         rstckren             ;  // RSTCKR          Enable
wire         ctrzinren            ;  // CTRLZINR        Enable  

// ------------------------------------------------------
// -- Register write enable wires
// ------------------------------------------------------  
wire         ccalrstnrwe          ;  // CCALRSTNR       Write Enable
wire         cclkdccenrwe         ;  // CCLKDCCEN       Write Enable
wire         casclkctrwe          ;  // CASCLKCTR       Write Enable
wire         ccaldccqecpirwe      ;  // CCALDCCQECPIR   Write Enable
wire         ccalqecctr1we        ;  // CCALQECCTR1     Write Enable
wire         ccaldccctr1we        ;  // CCALDCCCTR1     Write Enable
wire         ccalpictrwe          ;  // CCALPICTR       Write Enable
wire         ccalcrossctrwe       ;  // CCALCROSSCTR    Write Enable
wire         ccalrsvr0we          ;  // CCALRSVR0       Write Enable
wire         ccalrsvr1we          ;  // CCALRSVR1       Write Enable
wire         selck10gdrwe         ;  // SELCK10GDR      Write Enable
wire         selck2p5gdrwe        ;  // SELCK2P5GDR     Write Enable
wire         selck625mdrwe        ;  // SELCK625MDR     Write Enable
wire         p2sdataenrwe         ;  // P2SDATAENR      Write Enable
wire         enallprwe            ;  // ENALLPR         Write Enable
wire         enpiprwe             ;  // ENPIPR          Write Enable
wire         clkdivrstnrwe        ;  // CLKDIVRSTNR     Write Enable
wire         p2srsvr0we           ;  // P2SRSVR0        Write Enable
wire         p2srsvr1we           ;  // P2SRSVR1        Write Enable
wire         ckrxswrwe            ;  // CKRXSWR         Write Enable
wire         rstckrwe             ;  // RSTCKR          Write Enable
wire         ctrzinrwe            ;  // CTRLZINR        Write Enable
 

// ------------------------------------------------------
// -- Misc Registers
// ------------------------------------------------------        
wire  [0 :0] ccalrstnr          ;  // CCALRSTNR       Register, Default vaule is 1'b0                                     
wire  [4 :0] cclkdccenr         ;  // CCLKDCCEN       Register, Default vaule is 5'b0                                     
wire  [0 :0] casclkctr          ;  // CASCLKCTR       Register, Default vaule is 1'b1                                     
wire  [2 :0] ccaldccqecpir      ;  // CCALDCCQECPIR   Register, Default vaule is 3'b0                                     
wire  [19:0] ccalqecctr1        ;  // CCALQECCTR1     Register, Default vaule is {5'b10001,5'b10001,5'b10000,5'b10000}    
wire  [23:0] ccaldccctr1        ;  // CCALDCCCTR1     Register, Default vaule is {6'b111111,6'b000000,6'b111111,6'b000000}
wire  [23:0] ccalpictr          ;  // CCALPICTR       Register, Default vaule is {8'b11111111,8'b00000000,4'b0011,4'b0011}
wire  [5 :0] ccalcrossctr       ;  // CCALCROSSCTR    Register, Default vaule is {3'b100,3'b110}                          
wire  [31:0] ccalrsvr0          ;  // CCALRSVR0       Register, Default vaule is 32'h0                                    
wire  [31:0] ccalrsvr1          ;  // CCALRSVR1       Register, Default vaule is 32'h0                                    
wire  [3 :0] selck10gdr         ;  // SELCK10GDR      Register, Default vaule is 4'b0001                                  
wire  [3 :0] selck2p5gdr        ;  // SELCK2P5GDR     Register, Default vaule is 4'b0010                                  
wire  [8 :0] selck625mdr        ;  // SELCK625MDR     Register, Default vaule is 9'b100001010                             
wire  [15:0] p2sdataenr         ;  // P2SDATAENR      Register, Default vaule is 16'h1                                    
wire  [15:0] enallpr            ;  // ENALLPR         Register, Default vaule is 16'h1                                    
wire  [15:0] enpipr             ;  // ENPIPR          Register, Default vaule is 16'h1                                    
wire  [15:0] clkdivrstnr        ;  // CLKDIVRSTNR     Register, Default vaule is 16'h1                                    
wire  [31:0] p2srsvr0           ;  // P2SRSVR0        Register, Default vaule is 32'h0                                    
wire  [31:0] p2srsvr1           ;  // P2SRSVR1        Register, Default vaule is 32'h0                                    
wire  [15:0] ckrxswr            ;  // CKRXSWR         Register, Default vaule is 16'h1                                    
wire  [15:0] rstckr             ;  // RSTCKR          Register, Default vaule is 16'h1                                    
wire  [15:0] ctrzinr            ;  // CTRLZINR        Register, Default vaule is 16'h1                                    

reg  [31 :0] rddata_reg           ;

// ------------------------------------------------------
// -- Address decoder
//
//  Decodes the register address offset input(reg_addr)
//  to produce enable (select) signals for each of the
//  SW-registers in the macrocell. The reg_addr input  
//  is bits [15:0] of the paddr bus.                    
// ------------------------------------------------------
assign         ccalrstnren          = (rwaddr[7:2] == `CCALRSTNR     >>2) ? 1'b1 : 1'b0;  // CCALRSTNR       Enable
assign         cclkdccenren         = (rwaddr[7:2] == `CCLKDCCENR    >>2) ? 1'b1 : 1'b0;  // CCLKDCCEN       Enable
assign         casclkctren          = (rwaddr[7:2] == `CASCLKCTR     >>2) ? 1'b1 : 1'b0;  // CASCLKCTR       Enable
assign         ccaldccqecpiren      = (rwaddr[7:2] == `CCALDCCQECPIR >>2) ? 1'b1 : 1'b0;  // CCALDCCQECPIR   Enable
assign         ccalqecctr1en        = (rwaddr[7:2] == `CCALQECCTR1   >>2) ? 1'b1 : 1'b0;  // CCALQECCTR1     Enable
assign         ccaldccctr1en        = (rwaddr[7:2] == `CCALDCCCTR1   >>2) ? 1'b1 : 1'b0;  // CCALDCCCTR1     Enable
assign         ccalpictren          = (rwaddr[7:2] == `CCALPICTR     >>2) ? 1'b1 : 1'b0;  // CCALPICTR       Enable
assign         ccalcrossctren       = (rwaddr[7:2] == `CCALCROSSCTR  >>2) ? 1'b1 : 1'b0;  // CCALCROSSCTR    Enable
assign         ccalrsvr0en          = (rwaddr[7:2] == `CCALRSVR0     >>2) ? 1'b1 : 1'b0;  // CCALRSVR0       Enable
assign         ccalrsvr1en          = (rwaddr[7:2] == `CCALRSVR1     >>2) ? 1'b1 : 1'b0;  // CCALRSVR1       Enable
assign         selck10gdren         = (rwaddr[7:2] == `SELCK10GDR    >>2) ? 1'b1 : 1'b0;  // SELCK10GDR      Enable
assign         selck2p5gdren        = (rwaddr[7:2] == `SELCK2P5GDR   >>2) ? 1'b1 : 1'b0;  // SELCK2P5GDR     Enable
assign         selck625mdren        = (rwaddr[7:2] == `SELCK625MDR   >>2) ? 1'b1 : 1'b0;  // SELCK625MDR     Enable
assign         p2sdataenren         = (rwaddr[7:2] == `P2SDATAENR    >>2) ? 1'b1 : 1'b0;  // P2SDATAENR      Enable
assign         enallpren            = (rwaddr[7:2] == `ENALLPR       >>2) ? 1'b1 : 1'b0;  // ENALLPR         Enable
assign         enpipren             = (rwaddr[7:2] == `ENPIPR        >>2) ? 1'b1 : 1'b0;  // ENPIPR          Enable
assign         clkdivrstnren        = (rwaddr[7:2] == `CLKDIVRSTNR   >>2) ? 1'b1 : 1'b0;  // CLKDIVRSTNR     Enable
assign         p2srsvr0en           = (rwaddr[7:2] == `P2SRSVR0      >>2) ? 1'b1 : 1'b0;  // P2SRSVR0        Enable
assign         p2srsvr1en           = (rwaddr[7:2] == `P2SRSVR1      >>2) ? 1'b1 : 1'b0;  // P2SRSVR1        Enable
assign         ckrxswren            = (rwaddr[7:2] == `CKRXSWR       >>2) ? 1'b1 : 1'b0;  // CKRXSWR         Enable
assign         rstckren             = (rwaddr[7:2] == `RSTCKR        >>2) ? 1'b1 : 1'b0;  // RSTCKR          Enable
assign         ctrzinren            = (rwaddr[7:2] == `CTRLZINR      >>2) ? 1'b1 : 1'b0;  // CTRLZINR        Enable

// ------------------------------------------------------
// -- Write enable signals
//
//  Write enable signals for writable SW-registers.
//  The write enable for each register is the ANDed
//  result of the register enable and the input reg_wren
// ------------------------------------------------------ 
assign         ccalrstnrwe          = ccalrstnren     & wren; // CCALRSTNR       Write Enable
assign         cclkdccenrwe         = cclkdccenren    & wren; // CCLKDCCEN       Write Enable
assign         casclkctrwe          = casclkctren     & wren; // CASCLKCTR       Write Enable
assign         ccaldccqecpirwe      = ccaldccqecpiren & wren; // CCALDCCQECPIR   Write Enable
assign         ccalqecctr1we        = ccalqecctr1en   & wren; // CCALQECCTR1     Write Enable
assign         ccaldccctr1we        = ccaldccctr1en   & wren; // CCALDCCCTR1     Write Enable
assign         ccalpictrwe          = ccalpictren     & wren; // CCALPICTR       Write Enable
assign         ccalcrossctrwe       = ccalcrossctren  & wren; // CCALCROSSCTR    Write Enable
assign         ccalrsvr0we          = ccalrsvr0en     & wren; // CCALRSVR0       Write Enable
assign         ccalrsvr1we          = ccalrsvr1en     & wren; // CCALRSVR1       Write Enable
assign         selck10gdrwe         = selck10gdren    & wren; // SELCK10GDR      Write Enable
assign         selck2p5gdrwe        = selck2p5gdren   & wren; // SELCK2P5GDR     Write Enable
assign         selck625mdrwe        = selck625mdren   & wren; // SELCK625MDR     Write Enable
assign         p2sdataenrwe         = p2sdataenren    & wren; // P2SDATAENR      Write Enable
assign         enallprwe            = enallpren       & wren; // ENALLPR         Write Enable
assign         enpiprwe             = enpipren        & wren; // ENPIPR          Write Enable
assign         clkdivrstnrwe        = clkdivrstnren   & wren; // CLKDIVRSTNR     Write Enable
assign         p2srsvr0we           = p2srsvr0en      & wren; // P2SRSVR0        Write Enable
assign         p2srsvr1we           = p2srsvr1en      & wren; // P2SRSVR1        Write Enable
assign         ckrxswrwe            = ckrxswren       & wren; // CKRXSWR         Write Enable
assign         rstckrwe             = rstckren        & wren; // RSTCKR          Write Enable
assign         ctrzinrwe            = ctrzinren       & wren; // CTRLZINR        Write Enable


// ------------------------------------------------------
// -- ccalrstnr Register
//
//  Write ccalrstnr for 'CCALRSTNR' : 1-bit register
//  Register is split into the following bit fields
//
//  [0:0] --> ccalrstnr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(1) ccalrstnr_dfflrd (ccalrstnrdft, ccalrstnrwe, wrdata[0], ccalrstnr, clk, rstn);

// ------------------------------------------------------
// -- cclkdccenr Register
//
//  Write cclkdccenr for 'CCLKDCCEN' : 5-bit register
//  Register is split into the following bit fields
//
//  [4:0] --> cclkdccenr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(5) cclkdccenr_dfflrd (cclkdccenrdft, cclkdccenrwe, wrdata[4:0], cclkdccenr, clk, rstn);

// ------------------------------------------------------
// -- casclkctr Register
//
//  Write casclkctr for 'CASCLKCTR' : 1-bit register
//  Register is split into the following bit fields
//
//  [0:0] --> casclkctr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(1) casclkctr_dfflrd (casclkctrdft, casclkctrwe, wrdata[0], casclkctr, clk, rstn);

// ------------------------------------------------------
// -- ccaldccqecpir Register
//
//  Write ccaldccqecpir for 'CCALDCCQECPIR' : 3-bit register
//  Register is split into the following bit fields
//
//  [2:0] --> ccaldccqecpir 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(3) ccaldccqecpir_dfflrd (ccaldccqecpirdft, ccaldccqecpirwe, wrdata[2:0], ccaldccqecpir, clk, rstn);

// ------------------------------------------------------
// -- ccalqecctr1 Register
//
//  Write ccalqecctr1 for 'CCALQECCTR1' : 20-bit register
//  Register is split into the following bit fields
//
//  [19:0] --> ccalqecctr1 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(20) ccalqecctr1_dfflrd (ccalqecctr1dft, ccalqecctr1we, wrdata[19:0], ccalqecctr1, clk, rstn);

// ------------------------------------------------------
// -- ccaldccctr1 Register
//
//  Write ccaldccctr1 for 'CCALDCCCTR1' : 24-bit register
//  Register is split into the following bit fields
//
//  [23:0] --> ccaldccctr1 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(24) biasct3r_dfflrd (ccaldccctr1dft, ccaldccctr1we, wrdata[23:0], ccaldccctr1, clk, rstn);

// ------------------------------------------------------
// -- ccalpictr Register
//
//  Write ccalpictr for 'CCALPICTR' : 24-bit register
//  Register is split into the following bit fields
//
//  [23:0] --> ccalpictr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(24) ccalpictr_dfflrd (ccalpictrdft, ccalpictrwe, wrdata[23:0], ccalpictr, clk, rstn);

// ------------------------------------------------------
// -- ccalcrossctr Register
//
//  Write ccalcrossctr for 'CCALCROSSCTR' : 6-bit register
//  Register is split into the following bit fields
//
//  [5:0] --> ccalcrossctr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(6) ccalcrossctr_dfflrd (ccalcrossctrdft, ccalcrossctrwe, wrdata[5:0], ccalcrossctr, clk, rstn);

// ------------------------------------------------------
// -- ccalrsvr0 Register
//
//  Write ccalrsvr0 for 'CCALRSVR0' : 32-bit register
//  Register is split into the following bit fields
//
//  [31:0] --> ccalrsvr0 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(32) ccalrsvr0_dfflrd (ccalrsvr0dft, ccalrsvr0we, wrdata[31:0], ccalrsvr0, clk, rstn);

// ------------------------------------------------------
// -- ccalrsvr1 Register
//
//  Write ccalrsvr1 for 'CCALRSVR1' : 32-bit register
//  Register is split into the following bit fields
//
//  [31:0] --> ccalrsvr1 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(32) ccalrsvr1_dfflrd (ccalrsvr1dft, ccalrsvr1we, wrdata[31:0], ccalrsvr1, clk, rstn);


// ------------------------------------------------------
// -- selck10gdr Register
//
//  Write selck10gdr for 'SELCK10GDR' : 4-bit register
//  Register is split into the following bit fields
//
//  [3:0] --> selck10gdr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(4) selck10gdr_dfflrd (selck10gdrdft, selck10gdrwe, wrdata[3:0], selck10gdr, clk, rstn);

// ------------------------------------------------------
// -- selck2p5gdr Register
//
//  Write selck2p5gdr for 'SELCK2P5GDR' : 4-bit register
//  Register is split into the following bit fields
//
//  [3:0] --> selck2p5gdr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(4) selck2p5gdr_dfflrd (selck2p5gdrdft, selck2p5gdrwe, wrdata[3:0], selck2p5gdr, clk, rstn);


// ------------------------------------------------------
// -- selck625mdr Register
//
//  Write selck625mdr for 'SELCK625MDR' : 9-bit register
//  Register is split into the following bit fields
//
//  [8:0] --> selck625mdr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(9) selck625mdr_dfflrd (selck625mdrdft, selck625mdrwe, wrdata[8:0], selck625mdr, clk, rstn);


// ------------------------------------------------------
// -- p2sdataenr Register
//
//  Write p2sdataenr for 'P2SDATAENR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> p2sdataenr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) p2sdataenr_dfflrd (p2sdataenrdft, p2sdataenrwe, wrdata[15:0], p2sdataenr, clk, rstn);


// ------------------------------------------------------
// -- enallpr Register
//
//  Write enallpr for 'ENALLPR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> enallpr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) enallpr_dfflrd (enallprdft, enallprwe, wrdata[15:0], enallpr, clk, rstn);

// ------------------------------------------------------
// -- enpipr Register
//
//  Write enpipr for 'ENPIPR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> enpipr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) enpipr_dfflrd (enpiprdft, enpiprwe, wrdata[15:0], enpipr, clk, rstn);

// ------------------------------------------------------
// -- clkdivrstnr Register
//
//  Write clkdivrstnr for 'CLKDIVRSTNR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> clkdivrstnr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) clkdivrstnr_dfflrd (clkdivrstnrdft, clkdivrstnrwe, wrdata[15:0], clkdivrstnr, clk, rstn);

// ------------------------------------------------------
// -- p2srsvr0 Register
//
//  Write p2srsvr0 for 'P2SRSVR0' : 32-bit register
//  Register is split into the following bit fields
//
//  [31:0] --> p2srsvr0 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(32) p2srsvr0_dfflrd (p2srsvr0dft, p2srsvr0we, wrdata[31:0], p2srsvr0, clk, rstn);

// ------------------------------------------------------
// -- p2srsvr1 Register
//
//  Write p2srsvr1 for 'P2SRSVR1' : 32-bit register
//  Register is split into the following bit fields
//
//  [31:0] --> p2srsvr1 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(32) p2srsvr1_dfflrd (p2srsvr1dft, p2srsvr1we, wrdata[31:0], p2srsvr1, clk, rstn);


// ------------------------------------------------------
// -- ckrxswr Register
//
//  Write ckrxswr for 'CKRXSWR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> ckrxswr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) ckrxswr_dfflrd (ckrxswrdft, ckrxswrwe, wrdata[15:0], ckrxswr, clk, rstn);


// ------------------------------------------------------
// -- rstckr Register
//
//  Write rstckr for 'RSTCKR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> rstckr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) rstckr_dfflrd (rstckrdft, rstckrwe, wrdata[15:0], rstckr, clk, rstn);

// ------------------------------------------------------
// -- ctrzinr Register
//
//  Write ctrzinr for 'CTRLZINR' : 16-bit register
//  Register is split into the following bit fields
//
//  [15:0] --> ctrzinr 
// ------------------------------------------------------
sirv_gnrl_dfflrd #(16) ctrzinr_dfflrd (ctrzinrdft, ctrzinrwe, wrdata[15:0], ctrzinr, clk, rstn);

// ------------------------------------------------------
// -- Read data mux
//
// -- The data from the selected register is
// -- placed on a zero-padded 32-bit read data bus.
// ------------------------------------------------------
always @(*) begin : RDDATA_PROC
    rddata_reg = {32{1'b0}};
    if(ccalrstnren        == H )    rddata_reg[0 :0] = ccalrstnr[0 :0]     ;
    if(cclkdccenren       == H )    rddata_reg[4 :0] = cclkdccenr[4 :0]    ;
    if(casclkctren        == H )    rddata_reg[0 :0] = casclkctr[0 :0]     ;
    if(ccaldccqecpiren    == H )    rddata_reg[2 :0] = ccaldccqecpir[2 :0] ;
    if(ccalqecctr1en      == H )    rddata_reg[19:0] = ccalqecctr1[19:0]   ;
    if(ccaldccctr1en      == H )    rddata_reg[23:0] = ccaldccctr1[23:0]   ;
    if(ccalpictren        == H )    rddata_reg[23:0] = ccalpictr[23:0]     ;
    if(ccalcrossctren     == H )    rddata_reg[5 :0] = ccalcrossctr[5 :0]  ;
    if(ccalrsvr0en        == H )    rddata_reg[31:0] = ccalrsvr0[31:0]     ;
    if(ccalrsvr1en        == H )    rddata_reg[31:0] = ccalrsvr1[31:0]     ;
    if(selck10gdren       == H )    rddata_reg[3 :0] = selck10gdr[3 :0]    ;
    if(selck2p5gdren      == H )    rddata_reg[3 :0] = selck2p5gdr[3 :0]   ;
    if(selck625mdren      == H )    rddata_reg[8 :0] = selck625mdr[8 :0]   ;
    if(p2sdataenren       == H )    rddata_reg[15:0] = p2sdataenr[15:0]    ;
    if(enallpren          == H )    rddata_reg[15:0] = enallpr[15:0]       ;
    if(enpipren           == H )    rddata_reg[15:0] = enpipr[15:0]        ;
    if(clkdivrstnren      == H )    rddata_reg[15:0] = clkdivrstnr[15:0]   ;
    if(p2srsvr0en         == H )    rddata_reg[31:0] = p2srsvr0[31:0]      ;
    if(p2srsvr1en         == H )    rddata_reg[31:0] = p2srsvr1[31:0]      ;
    if(ckrxswren          == H )    rddata_reg[15:0] = ckrxswr[15:0]       ;
    if(rstckren           == H )    rddata_reg[15:0] = rstckr[15:0]        ;
    if(ctrzinren          == H )    rddata_reg[15:0] = ctrzinr[15:0]       ;
end

//rddata
sirv_gnrl_dffr #(32) rddata_dffr (rddata_reg, rddata, clk, rstn);

// ------------------------------------------------------
// -- Output signals assignment
// ------------------------------------------------------
assign CcalRstn       = ccalrstnr           ;
assign EnAllP         = cclkdccenr          ;
assign DccEn          = casclkctr           ;
assign CasGateCkCtrl  = casclkctr           ; 
assign SpiEnPi        = ccaldccqecpir[2]    ;
assign SpiEnQec       = ccaldccqecpir[1]    ;
assign SpiEnDcc       = ccaldccqecpir[0]    ;
assign SpiQecCtrlIp   = ccalqecctr1[19:15]  ; 
assign SpiQecCtrlIn   = ccalqecctr1[14:10]  ;
assign SpiQecCtrlQp   = ccalqecctr1[9 : 5]  ;
assign SpiQecCtrlQn   = ccalqecctr1[4 : 0]  ;
                                            
assign SpiDccCtrlIup  = ccaldccctr1[23:18]  ;
assign SpiDccCtrlIdn  = ccaldccctr1[17:12]  ;
assign SpiDccCtrlQup  = ccaldccctr1[11: 6]  ;
assign SpiDccCtrlQdn  = ccaldccctr1[5 : 0]  ;
                      
assign SpiSiqNOut     = ccalpictr[23:16]    ; 
assign SpiSiqPOut     = ccalpictr[15: 8]    ;
assign SpiSiPOut      = ccalpictr[7 : 4]    ;
assign SpiSqPOut      = ccalpictr[3 : 0]    ;
  
assign CrtlCrossOverN = ccalcrossctr[5:3]   ;
assign CrtlCrossOverP = ccalcrossctr[2:0]   ;
assign CcalRsv0       = ccalrsvr0           ;
assign CcalRsv1       = ccalrsvr0           ;
  
assign SelCk10GDig    = selck10gdr          ;
assign SelCk2p5GDig   = selck2p5gdr         ;
assign SelCk625MDig   = selck625mdr         ;
assign P2sDataEn      = p2sdataenr          ;
assign P2sEnAllP      = enallpr             ;
assign EnPiP          = enpipr              ;
assign CkDivRstn      = clkdivrstnr         ;
assign p2srsv0        = p2srsvr0            ;
assign p2srsv1        = p2srsvr1            ;
assign CkRxSw         = ckrxswr             ;
assign RstnCk         = rstckr              ;
assign CtrlZin        = ctrzinr             ; 
 
endmodule

`undef CCALRSTNR     
`undef CCLKDCCENR    
`undef CASCLKCTR     
`undef CCALDCCQECPIR 
`undef CCALQECCTR1   
`undef CCALDCCCTR1   
`undef CCALPICTR     
`undef CCALCROSSCTR  
`undef CCALRSVR0     
`undef CCALRSVR1     
`undef SELCK10GDR    
`undef SELCK2P5GDR   
`undef SELCK625MDR   
`undef P2SDATAENR    
`undef ENALLPR       
`undef ENPIPR        
`undef CLKDIVRSTNR   
`undef P2SRSVR0      
`undef P2SRSVR1      
`undef CKRXSWR       
`undef RSTCKR        
`undef CTRLZINR      
`undef VERSIONR         

