`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/07/03 13:29:31
// Design Name: 
// Module Name: xil_tdpram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
//`define XINLINX_FPGA

module xil_tdpram #(
   parameter DATAWIDTH = 32 
  ,parameter ADDRWIDTH = 12
)(
   input                       PortClk
  ,input  [ADDRWIDTH-1     :0] PortAAddr
  ,input  [DATAWIDTH-1     :0] PortADataIn
  ,input                       PortAWriteEnable      //active low
  ,input                       PortAChipEnable       //active low
  ,input  [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable  //active low
  ,output [DATAWIDTH-1     :0] PortADataOut
  
  ,input  [ADDRWIDTH-1     :0] PortBAddr
  ,input  [DATAWIDTH-1     :0] PortBDataIn
  ,input                       PortBWriteEnable      //active low
  ,input                       PortBChipEnable       //active low
  ,input  [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable  //active low
  ,output [DATAWIDTH-1     :0] PortBDataOut
  );
////////////////////////////////////////////////////////////////////////////////
//Function
////////////////////////////////////////////////////////////////////////////////  	
function integer clog2(input integer bit_depth);
  begin
    for(clog2=0;bit_depth>0;clog2=clog2+1)
      bit_depth =bit_depth>>1;
  end
endfunction

localparam LSB  = clog2(DATAWIDTH/8 -1);
localparam MAW  = ADDRWIDTH - LSB;
localparam MB   =(DATAWIDTH)*(32'h0000_0001<<MAW);
////////////////////////////////////////////////////////////////////////////////
//XPM
////////////////////////////////////////////////////////////////////////////////
wire [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable_w = {(DATAWIDTH/8){PortAWriteEnable | PortAChipEnable}} | PortAByteWriteEnable;
wire [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable_w = {(DATAWIDTH/8){PortBWriteEnable | PortBChipEnable}} | PortBByteWriteEnable;
xpm_memory_tdpram                          #(
   .CLOCKING_MODE                           ( "common_clock"                          ) // String
  ,.ECC_MODE                                ( "no_ecc"                                ) // String
  ,.MEMORY_INIT_FILE                        ( "none"                                  ) // String
  ,.MEMORY_INIT_PARAM                       ( "0"                                     ) // String
  ,.MEMORY_OPTIMIZATION                     ( "true"                                  ) // String
  ,.MEMORY_PRIMITIVE                        ( "auto"                                  ) // String
  ,.AUTO_SLEEP_TIME                         ( 0                                       ) // DECIMAL
  ,.CASCADE_HEIGHT                          ( 0                                       ) // DECIMAL
  ,.SIM_ASSERT_CHK                          ( 0                                       ) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
  ,.USE_EMBEDDED_CONSTRAINT                 ( 0                                       ) // DECIMAL
  ,.USE_MEM_INIT                            ( 1                                       ) // DECIMAL
  ,.WAKEUP_TIME                             ( "disable_sleep"                         ) // String
  ,.MESSAGE_CONTROL                         ( 0                                       ) // DECIMAL
  ,.MEMORY_SIZE                             ( MB                                      ) // DECIMAL
	  
  ,.ADDR_WIDTH_A                            ( MAW                                     ) // DECIMAL
  ,.BYTE_WRITE_WIDTH_A                      ( 8                                       ) // DECIMAL
  ,.WRITE_DATA_WIDTH_A                      ( DATAWIDTH                               ) // DECIMAL
  ,.READ_DATA_WIDTH_A                       ( DATAWIDTH                               ) // DECIMAL
  ,.READ_LATENCY_A                          ( 1                                       ) // DECIMAL
  ,.READ_RESET_VALUE_A                      ( "0"                                     ) // String
  ,.RST_MODE_A                              ( "SYNC"                                  ) // String
  ,.WRITE_MODE_A                            ( "no_change"                             ) // String
  
  ,.ADDR_WIDTH_B                            ( MAW                                     ) // DECIMAL
  ,.BYTE_WRITE_WIDTH_B                      ( 8                                       ) // DECIMAL
  ,.WRITE_DATA_WIDTH_B                      ( DATAWIDTH                               ) // DECIMAL
  ,.READ_DATA_WIDTH_B                       ( DATAWIDTH                               ) // DECIMAL
  ,.READ_LATENCY_B                          ( 1                                       ) // DECIMAL
  ,.READ_RESET_VALUE_B                      ( "0"                                     ) // String
  ,.RST_MODE_B                              ( "SYNC"                                  ) // String
  ,.WRITE_MODE_B                            ( "no_change"                             ) // String
  ) xpm_memory_tdpram_inst                  (              
	                                                                                  
   .rsta                                    ( 0                                       ) // 1-bit input: Reset signal for the final port A output register stage. 
                                                                                        // Synchronously resets output port douta to the value specified by
                                                                                        // parameter READ_RESET_VALUE_A. 
  ,.clka                                    ( PortClk                                 ) // 1-bit input: Clock signal for port A. Also clocks port B when 
                                                                                        // parameter CLOCKING_MODE is "common_clock".
  ,.regcea                                  ( 0                                       ) // 1-bit input: Clock Enable for the last register stage on the output
                                                                                        // data path.
  ,.ena                                     ( 1'b1                                    ) // 1-bit input: Memory enable signal for port A. Must be high on clock
                                                                                        // cycles when read or write operations are initiated. Pipelined
																						// internally.
  ,.wea                                     ( ~PortAByteWriteEnable_w                 ) // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                                                                                        // for port A input data port dina. 1 bit wide when word-wide writes are
                                                                                        // used. In byte-wide write configurations, each bit controls the
                                                                                        // writing one byte of dina to address addra. For example, to
                                                                                        // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
                                                                                        // is 32, wea would be 4'b0010.
  ,.addra                                   ( PortAAddr[ADDRWIDTH-1 : LSB]            ) // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
  ,.dina                                    ( PortADataIn                             ) // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.           
  ,.douta                                   ( PortADataOut                            ) // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.                                
  ,.dbiterra                                (                                         ) // 1-bit output: Status signal to indicate double bit error occurrence
                                                                                        // on the data output of port A.
  ,.sbiterra                                (                                         ) // 1-bit output: Status signal to indicate single bit error occurrence
                                                                                        // on the data output of port A.														  
  ,.injectdbiterra                          ( 1'b0                                    ) // 1-bit input: Controls double bit error injection on input data when
                                                                                        // ECC enabled (Error injection capability is not available in
																						// "decode_only" mode).
  ,.injectsbiterra                          ( 1'b0                                    ) // 1-bit input: Controls single bit error injection on input data when
                                                                                        // ECC enabled (Error injection capability is not available in                                  
                                                                                        // "decode_only" mode). 

  ,.rstb                                    ( 0                                       ) // 1-bit input: Reset signal for the final port B output register stage. 
                                                                                        // Synchronously resets output port douta to the value specified by
                                                                                        // parameter READ_RESET_VALUE_B. 
  ,.clkb                                    ( PortClk                                 ) // 1-bit input: Clock signal for port B. Also clocks port A when 
                                                                                        // parameter CLOCKING_MODE is "common_clock".
  ,.regceb                                  ( 0                                       ) // 1-bit input: Clock Enable for the last register stage on the output
                                                                                        // data path.
  ,.enb                                     ( 1'b1                                    ) // 1-bit input: Memory enable signal for port B. Must be high on clock
                                                                                        // cycles when read or write operations are initiated. Pipelined
																						// internally.
  ,.web                                     ( ~PortBByteWriteEnable_w                 ) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
                                                                                        // for port B input data port dina. 1 bit wide when word-wide writes are
                                                                                        // used. In byte-wide write configurations, each bit controls the
                                                                                        // writing one byte of dinb to address addrb. For example, to
                                                                                        // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_B
                                                                                        // is 32, wea would be 4'b0010.
  ,.addrb                                   ( PortBAddr[ADDRWIDTH-1 : LSB]            ) // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
  ,.dinb                                    ( PortBDataIn                             ) // WRITE_DATA_WIDTH_A-bit input: Data input for port B write operations.           
  ,.doutb                                   ( PortBDataOut                            ) // READ_DATA_WIDTH_A-bit output: Data output for port B read operations.                                
  ,.dbiterrb                                (                                                                                 ) // 1-bit output: Status signal to indicate double bit error occurrence
                                                                                        // on the data output of port B.
  ,.sbiterrb                                (                                         ) // 1-bit output: Status signal to indicate single bit error occurrence
                                                                                        // on the data output of port B.														  
  ,.injectdbiterrb                          ( 1'b0                                    ) // 1-bit input: Controls double bit error injection on input data when
                                                                                        // ECC enabled (Error injection capability is not available in
																						// "decode_only" mode).
  ,.injectsbiterrb                          ( 1'b0                                    ) // 1-bit input: Controls single bit error injection on input data when
                                                                                        // ECC enabled (Error injection capability is not available in                                  
                                                                                        // "decode_only" mode).                   																						
  ,.sleep                                   ( 1'b0                                    ) // 1-bit input: sleep signal to enable the dynamic power saving feature.								   
   );
endmodule
