`timescale 1ns / 1ps

module clock_tb #(
    parameter PERIOD = 4,
    parameter PHASE  = 0
    )(
    output clk_out
    );
    reg clk;

    initial begin
        //#PHASE clk = 0;
        clk = 0;
        forever #(PERIOD/2.0) clk = ~clk;
    end
    assign clk_out = clk;
endmodule
/* HIDE```*/
