
`include "../define/chip_define.v"
//`define TSMC_INITIALIZE_MEM
module dpram #(
   parameter DATAWIDTH = 32
  ,parameter ADDRWIDTH = 13
)(
   input                       PortClk
  ,input  [ADDRWIDTH-1     :0] PortAAddr
  ,input  [DATAWIDTH-1     :0] PortADataIn
  ,input                       PortAWriteEnable      //active low
  ,input                       PortAChipEnable       //active low
  ,input  [(DATAWIDTH/8)-1 :0] PortAByteWriteEnable  //active low
  ,output [DATAWIDTH-1     :0] PortADataOut
  
  ,input  [ADDRWIDTH-1     :0] PortBAddr
  ,input  [DATAWIDTH-1     :0] PortBDataIn
  ,input                       PortBWriteEnable      //active low
  ,input                       PortBChipEnable       //active low
  ,input  [(DATAWIDTH/8)-1 :0] PortBByteWriteEnable  //active low
  ,output [DATAWIDTH-1     :0] PortBDataOut
);

//==================================================================================
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//==================================================================================

`ifdef BEHAVIOR_SIM
  dpram_model                              #(
     .DATAWIDTH                             ( DATAWIDTH                               )
    ,.ADDRWIDTH                             ( ADDRWIDTH                               )             
  ) dpram_model                             (                                         
     .PortClk                               ( PortClk                                 )
    ,.PortAWriteEnable                      ( PortAWriteEnable                        )
	,.PortAChipEnable                       ( PortAChipEnable                         )
    ,.PortAByteWriteEnable                  ( PortAByteWriteEnable                    )
    ,.PortAAddr                             ( PortAAddr                               )
    ,.PortADataIn                           ( PortADataIn                             )
    ,.PortADataOut                          ( PortADataOut                            )
    ,.PortBWriteEnable                      ( PortBWriteEnable                        )
	,.PortBChipEnable                       ( PortBChipEnable                         )
    ,.PortBByteWriteEnable                  ( PortBByteWriteEnable                    )
    ,.PortBAddr                             ( PortBAddr                               )
    ,.PortBDataIn                           ( PortBDataIn                             )
    ,.PortBDataOut                          ( PortBDataOut                            )
  );
`elsif XILINX_FPGA
  xil_tdpram                               #(
   .DATAWIDTH                               ( DATAWIDTH                               )
  ,.ADDRWIDTH                               ( ADDRWIDTH                               )
  ) U_xil_tdpram                            (
   .PortClk                                 ( PortClk                                 )
  ,.PortAAddr                               ( PortAAddr                               )
  ,.PortADataIn                             ( PortADataIn                             )
  ,.PortAWriteEnable                        ( PortAWriteEnable                        )
  ,.PortAChipEnable                         ( PortAChipEnable                         )
  ,.PortAByteWriteEnable                    ( PortAByteWriteEnable                    )
  ,.PortADataOut                            ( PortADataOut                            )
  ,.PortBAddr                               ( PortBAddr                               )
  ,.PortBDataIn                             ( PortBDataIn                             )
  ,.PortBWriteEnable                        ( PortBWriteEnable                        )
  ,.PortBChipEnable                         ( PortBChipEnable                         )
  ,.PortBByteWriteEnable                    ( PortBByteWriteEnable                    )
  ,.PortBDataOut                            ( PortBDataOut                            )
  );
`elsif TSMC_IC
  tsmc_dpram                               #(
   .DATAWIDTH                               ( DATAWIDTH                               )
  ,.ADDRWIDTH                               ( ADDRWIDTH                               )
  ) U_tsmc_dpram                            (
   .PortClk                                 ( PortClk                                 )
  ,.PortAAddr                               ( PortAAddr                               )
  ,.PortADataIn                             ( PortADataIn                             )
  ,.PortAWriteEnable                        ( PortAWriteEnable                        )
  ,.PortAChipEnable                         ( PortAChipEnable                         )
  ,.PortAByteWriteEnable                    ( PortAByteWriteEnable                    )
  ,.PortADataOut                            ( PortADataOut                            )
  ,.PortBAddr                               ( PortBAddr                               )
  ,.PortBDataIn                             ( PortBDataIn                             )
  ,.PortBWriteEnable                        ( PortBWriteEnable                        )
  ,.PortBChipEnable                         ( PortBChipEnable                         )
  ,.PortBByteWriteEnable                    ( PortBByteWriteEnable                    )
  ,.PortBDataOut                            ( PortBDataOut                            )
  );	
`endif


endmodule

`include "../define/chip_undefine.v"