`timescale 1ns / 1ps

module uart_byte_tx_tb();

    reg Clk;
    reg Reset_n;
    reg [7:0]Data;
    reg Send_Go;
    wire uart_tx;
    wire Tx_Done;    

    uart_byte_tx uart_byte_tx(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .Data(Data),
        .uart_tx(uart_tx),
        .Send_Go(Send_Go),
        .Tx_Done(Tx_Done)
    );
//    defparam uart_byte_tx.MCNT_DLY = 50_000_0 - 1;
    
    initial Clk = 1;
    always #10 Clk = ~Clk;
    
    initial begin
        Reset_n = 0;
        #200;
        Reset_n = 1;
        Data = 8'b0101_0101;
        Send_Go = 1 ;
        #20;
        Send_Go = 0;
        #20;
        #30000000;
        Data = 8'b1010_1010;
        Send_Go = 1 ;
        #20;
        Send_Go = 0;
        #20;
        #30000000;
        $stop;    
    end

endmodule
