//`timescale 1ns / 1ns
module tb();
     bit clk;
     bit clk_enable;
     bit reset;
     real data[8];
     real i_data[8];
     real q_data[8];

initial
begin
     $fsdbDumpfile("TB.fsdb");
     $fsdbDumpvars(0, tb);
end


initial	begin
		#0;
		reset = 1'b1;
		#100;
		reset = 1'b0;				
end
//clk
initial	begin
		#0;
		clk = 1'b1;			
end
always #5 clk = ~clk;

initial begin
	#0;
	clk_enable = 1'b1;
end

 	logic [21:0]	cnt;
always@(posedge clk or negedge reset)begin
		if(reset)
			cnt	<=	22'd0;
		else
			cnt	<=	cnt + 22'd1;
end
initial	begin
	wait(cnt[14]==1'b1)
			$finish(0);
end

logic [10:0] i=0;
always@(posedge clk or negedge reset)begin
		if(reset&(i==11'd8))begin
			i	<=	11'b0;
		end else begin
			i	<=	i+1'b1;
		end
end

real data_reg[7:0];
always@(posedge clk or negedge reset)begin
	data_reg[i] <= 64'b0+i;
end



hilbert_fir_dpi inst_hilbert_fir_dpi(
.clk(clk),
.clk_enable(clk_enable),
.reset(reset),
.data(data_reg),
.i_data(i_data),
.q_data(q_data)
);
initial begin
#160000
$display("data_reg is:%d%d%d%d%d%d%d%d",data_reg[0],data_reg[1],data_reg[2],data_reg[3],data_reg[4],data_reg[5],data_reg[6],data_reg[7]);

$display("i_data_temp is :",inst_hilbert_fir_dpi.i_data_temp[1]);

$display("i_data0 is :",i_data[0]);
$display("i_data1 is :",i_data[1]);
$display("i_data2 is :",i_data[2]);
$display("i_data3 is :",i_data[3]);
$display("i_data4 is :",i_data[4]);
$display("i_data5 is :",i_data[5]);
$display("i_data6 is :",i_data[6]);
$display("i_data7 is :",i_data[7]);

$display("q_data0 is :",q_data[0]);
$display("q_data1 is :",q_data[1]);
$display("q_data2 is :",q_data[2]);
$display("q_data3 is :",q_data[3]);
$display("q_data4 is :",q_data[4]);
$display("q_data5 is :",q_data[5]);
$display("q_data6 is :",q_data[6]);
$display("q_data7 is :",q_data[7]);
end

endmodule

