Command: /home/yzzhang/work/hdl/readout_chip/up/EZQ_readout/testbench/refm/hilbert_dpi/codegen/dll/hilbert_fir/./simv +vcs+loopreport -sv_lib DPI_Component -l sim.log
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Apr  3 13:13 2025
UVM_INFO /opt/synopsys/vcs-mx/O-2018.09-SP2/etc/uvm-1.2/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES] 
----------------------------------------------------------------
UVM-1.2.Synopsys
(C) 2007-2014 Mentor Graphics Corporation
(C) 2007-2014 Cadence Design Systems, Inc.
(C) 2006-2014 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
(C) 2013-2014 NVIDIA Corporation
----------------------------------------------------------------

  ***********       IMPORTANT RELEASE NOTES         ************

  You are using a version of the UVM library that has been compiled
  with `UVM_NO_DEPRECATED undefined.
  See http://www.eda.org/svdb/view.php?id=3313 for more details.

  You are using a version of the UVM library that has been compiled
  with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
  See http://www.eda.org/svdb/view.php?id=3770 for more details.

      (Specify +UVM_NO_RELNOTES to turn off this notice)

*Verdi* Loading libsscore_vcs201712.so
FSDB Dumper for VCS, Release Verdi_N-2017.12-SP2, Linux x86_64/64bit, 05/27/2018
(C) 1996 - 2018 by Synopsys, Inc.
***********************************************************************
*  ERROR -                                                            *
*  The simulator version is newer than the FSDB dumper version which  *
*  may cause abnormal behavior, please contact Synopsys support for   *
*  assistance.                                                        *
***********************************************************************
*Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi* : Create FSDB file 'TB.fsdb'
*Verdi* : Begin traversing the scope (tb), layer (0).
*Verdi* : End of traversing.
data_reg is:                   3                   4                   5                   6                   7                   8                   9                  10
i_data0 is :3
i_data1 is :4
i_data2 is :5
i_data3 is :6
i_data4 is :7
i_data5 is :8
i_data6 is :9
i_data7 is :10
q_data0 is :-6
q_data1 is :-4
q_data2 is :-4
q_data3 is :-3
q_data4 is :-3
q_data5 is :0
q_data6 is :0
q_data7 is :7
           V C S   S i m u l a t i o n   R e p o r t 
Time: 163930
