28 lines
1.0 KiB
Plaintext
28 lines
1.0 KiB
Plaintext
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flowchart LR
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C["公共 12 GHz 时钟源"]
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HC["主机侧分频与分配<br/>/32 → 375 MHz；/64 → 187.5 MHz"]
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SC["从机侧分频与分配<br/>每个从机 /16 → 750 MHz"]
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M["主机 Master FPGA<br/>375 MHz DDR 串行<br/>187.5 MHz × 4 bit"]
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S1["从机 1 · Slave ASIC<br/>750 MHz SDR<br/>1 个 RX + 1 个 TX"]
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S2["从机 2 · Slave ASIC<br/>750 MHz SDR<br/>1 个 RX + 1 个 TX"]
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SN["… 更多从机<br/>每台同样 1 个 RX + 1 个 TX"]
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C --> HC --> M
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C --> SC
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SC --> S1
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SC --> S2
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SC --> SN
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M -- "TX_1 → RX · 1 对 LVDS · 750 Mbps" --> S1
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S1 -- "TX → RX_1 · 1 对 LVDS · 750 Mbps" --> M
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M -- "TX_2 → RX · 1 对 LVDS · 750 Mbps" --> S2
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S2 -- "TX → RX_2 · 1 对 LVDS · 750 Mbps" --> M
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M <-->|"每台同样两对 LVDS"| SN
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classDef clock fill:#e9effb,stroke:#6d84ba,color:#244475;
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classDef master fill:#e6f4f4,stroke:#087f8c,color:#175660;
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classDef slave fill:#fff0e3,stroke:#d7722d,color:#84502d;
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class C,HC,SC clock;
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class M master;
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class S1,S2,SN slave;
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