diff --git a/attach/.gitkeep b/attach/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/attach/LVDS封装与解析示意图.mmd b/attach/LVDS封装与解析示意图.mmd
deleted file mode 100644
index 3adc0c3..0000000
--- a/attach/LVDS封装与解析示意图.mmd
+++ /dev/null
@@ -1,29 +0,0 @@
-flowchart TB
- subgraph TX[发送端：封装]
- direction TB
- T0[DATA / CFG / CTRL：字段及长度检查] --> T1[形成明文 SOF、字段和载荷]
- T1 --> T2[CRC32 覆盖 SOF、字段和载荷；追加 CRC]
- T2 --> TS[SOF 原样发送]
- T2 --> TB[SOF 后的主体逐帧加扰：字段、载荷、CRC]
- TB --- TN[每帧加载 58 个 1；帧内连续推进状态]
- TS --> TM[串接为完整帧；帧内不可插入 IDLE]
- TB --> TM
- TF[TRAIN / TRAIN_ACK / SYNC / SYNC_ACK / SYNC_RESET：SOF + PRBS7_128] --> TM
- TI[IDLE32：完整固定码字] --> TM
- end
- TM --> W[750 Mbps 连续串行流；4-byte 对齐；每字节 bit0 先发]
- subgraph RX[接收端：解析]
- direction TB
- R0[在已有字对齐基础上，仅在帧边界匹配原始标记]
- R0 --> RB[DATA / CFG / CTRL：记录 SOF，初始化解扰状态]
- RB --> RD[解扰主体；检查 LEN 并按长度计数；CTRL 为固定长度]
- RD --> RC[CRC32：原始 SOF + 解扰字段和载荷；比较收到的 CRC]
- RC --> RV[CRC 与字段格式均通过：输出完整候选帧]
- RC --> RE[校验 / 字段失败：报告错误，不提交]
- R0 --> RF[固定同步帧：比较完整 160 bit；IDLE：比较完整 32 bit]
- RF --> RP[输出匹配结果；不执行同步状态切换]
- R0 --> RU[未知边界标记：报告 boundary_error]
- end
- W --> R0
- RV --> EXT[外部控制逻辑：决定序号接受和动作执行]
- RP --> EXT
diff --git a/attach/LVDS封装与解析示意图.png b/attach/LVDS封装与解析示意图.png
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index c500f1a..0000000
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diff --git a/attach/LVDS封装与解析示意图.svg b/attach/LVDS封装与解析示意图.svg
deleted file mode 100644
index 3ebddd1..0000000
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-
\ No newline at end of file
diff --git a/attach/LVDS物理环境.svg b/attach/LVDS物理环境.svg
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-
-
-
-
\ No newline at end of file
diff --git a/attach/LVDS物理环境示意图.mmd b/attach/LVDS物理环境示意图.mmd
deleted file mode 100644
index 224ccc1..0000000
--- a/attach/LVDS物理环境示意图.mmd
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@@ -1,27 +0,0 @@
-flowchart LR
- C["公共 12 GHz 时钟源"]
- HC["主机侧分频与分配
/32 → 375 MHz；/64 → 187.5 MHz"]
- SC["从机侧分频与分配
每个从机 /16 → 750 MHz"]
- M["主机 Master FPGA
375 MHz DDR 串行
187.5 MHz × 4 bit"]
- S1["从机 1 · Slave ASIC
750 MHz SDR
1 个 RX + 1 个 TX"]
- S2["从机 2 · Slave ASIC
750 MHz SDR
1 个 RX + 1 个 TX"]
- SN["… 更多从机
每台同样 1 个 RX + 1 个 TX"]
-
- C --> HC --> M
- C --> SC
- SC --> S1
- SC --> S2
- SC --> SN
-
- M -- "TX_1 → RX · 1 对 LVDS · 750 Mbps" --> S1
- S1 -- "TX → RX_1 · 1 对 LVDS · 750 Mbps" --> M
- M -- "TX_2 → RX · 1 对 LVDS · 750 Mbps" --> S2
- S2 -- "TX → RX_2 · 1 对 LVDS · 750 Mbps" --> M
- M <-->|"每台同样两对 LVDS"| SN
-
- classDef clock fill:#e9effb,stroke:#6d84ba,color:#244475;
- classDef master fill:#e6f4f4,stroke:#087f8c,color:#175660;
- classDef slave fill:#fff0e3,stroke:#d7722d,color:#84502d;
- class C,HC,SC clock;
- class M master;
- class S1,S2,SN slave;
diff --git a/attach/LVDS物理环境示意图.png b/attach/LVDS物理环境示意图.png
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diff --git a/attach/LVDS物理环境示意图.svg b/attach/LVDS物理环境示意图.svg
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-