flowchart LR
    C["公共 12 GHz 时钟源"]
    HC["主机侧分频与分配<br/>/32 → 375 MHz；/64 → 187.5 MHz"]
    SC["从机侧分频与分配<br/>每个从机 /16 → 750 MHz"]
    M["主机 Master FPGA<br/>375 MHz DDR 串行<br/>187.5 MHz × 4 bit"]
    S1["从机 1 · Slave ASIC<br/>750 MHz SDR<br/>1 个 RX + 1 个 TX"]
    S2["从机 2 · Slave ASIC<br/>750 MHz SDR<br/>1 个 RX + 1 个 TX"]
    SN["… 更多从机<br/>每台同样 1 个 RX + 1 个 TX"]

    C --> HC --> M
    C --> SC
    SC --> S1
    SC --> S2
    SC --> SN

    M -- "TX_1 → RX · 1 对 LVDS · 750 Mbps" --> S1
    S1 -- "TX → RX_1 · 1 对 LVDS · 750 Mbps" --> M
    M -- "TX_2 → RX · 1 对 LVDS · 750 Mbps" --> S2
    S2 -- "TX → RX_2 · 1 对 LVDS · 750 Mbps" --> M
    M <-->|"每台同样两对 LVDS"| SN

    classDef clock fill:#e9effb,stroke:#6d84ba,color:#244475;
    classDef master fill:#e6f4f4,stroke:#087f8c,color:#175660;
    classDef slave fill:#fff0e3,stroke:#d7722d,color:#84502d;
    class C,HC,SC clock;
    class M master;
    class S1,S2,SN slave;